r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 186

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 6 User Break Controller (UBC)
6.3.2
BAMR is a 32-bit readable/writable register. BAMR specifies bits masked in the break address
bits specified by BAR. BAMR is initialized to H'00000000 by a power-on reset, but retains its
previous value by a manual reset or in software standby mode or sleep mode.
Rev. 2.00 Dec. 09, 2005 Page 162 of 1152
REJ09B0191-0200
Bit
31 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Break Address Mask Register (BAMR)
BAM31 BAM30 BAM29 BAM28 BAM27 BAM26 BAM25 BAM24 BAM23 BAM22 BAM21 BAM20 BAM19 BAM18 BAM17 BAM16
BAM15 BAM14 BAM13 BAM12 BAM11 BAM10 BAM9 BAM8 BAM7 BAM6 BAM5 BAM4 BAM3 BAM2 BAM1 BAM0
Bit Name
BAM31 to
BAM0
R/W
R/W
31
15
0
0
R/W
R/W
30
14
0
0
R/W
R/W
29
13
0
0
Initial
Value
All 0
R/W
R/W
28
12
0
0
R/W
R/W
27
11
0
0
R/W
R/W
R/W
R/W
26
10
0
0
Description
Break Address Mask
Specify bits masked in the break address bits specified
by BAR (BA31 to BA0).
0: Break address bit BAn is included in the break
1: Break address bit BAn is masked and not included
Note: n = 31 to 0
R/W
R/W
25
0
9
0
condition
in the break condition
R/W
R/W
24
0
8
0
R/W
R/W
23
0
7
0
R/W
R/W
22
0
6
0
R/W
R/W
21
0
5
0
R/W
R/W
20
0
4
0
R/W
R/W
19
0
3
0
R/W
R/W
18
0
2
0
R/W
R/W
17
0
1
0
R/W
R/W
16
0
0
0