r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 484

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
10.3.9
TSYCR is an 8-bit readable/writable register that specifies conditions for clearing TCNT_3 and
TCNT_4 in the MTU2S in synchronization with the MTU2. The MTU2S has one TSYCR in
channel 3 but the MTU2 has no TSYCR.
Rev. 2.00 Dec. 09, 2005 Page 460 of 1152
REJ09B0191-0200
Bit
0
Bit
7
6
Bit Name
I1AE
Bit Name
CE0A
CE0B
Timer Synchronous Clear Register (TSYCR)
Initial value:
Initial
Value
0
Initial
Value
0
0
R/W:
Bit:
CE0A
R/W
7
0
R/W
R/W
R/W
R/W
R/W
CE0B
R/W
6
0
Description
Input Capture Enable
Specifies whether to include the TIOC1A pin in the
TGRA_2 input capture conditions.
0: Does not include the TIOC1A pin in the TGRA_2
1: Includes the TIOC1A pin in the TGRA_2 input
Description
Clear Enable 0A
Enables or disables counter clearing when the TGFA
flag of TSR_0 in the MTU2 is set.
0: Disables counter clearing by the TGFA flag in TSR_0
1: Enables counter clearing by the TGFA flag in TSR_0
Clear Enable 0B
Enables or disables counter clearing when the TGFB
flag of TSR_0 in the MTU2 is set.
0: Disables counter clearing by the TGFB flag in TSR_0
1: Enables counter clearing by the TGFB flag in TSR_0
CE0C
R/W
5
0
capture conditions
input capture conditions
CE0D
R/W
4
0
CE1A
R/W
3
0
CE1B
R/W
2
0
CE2A
R/W
1
0
CE2B
R/W
0
0