r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 219

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

(3)
ways for the entry specified by the address field are compared with the tag address that is specified
by the data field. Write the U bit (only for operand cache) and the V bit specified by the data field
to the entry of the way that has a hit. However, the tag address and LRU bits remain unchanged.
When there is no way that has a hit, nothing is written and there is no operation.
This function is used to invalidate a specific entry in the cache. When the U bit of the entry that
has had a hit is 1 in the operand cache, writing back should be performed. However, when 0 is
written to the V bit, 0 must also be written to the U bit of that entry.
7.4.2
To access a data array, the 32-bit address field (for read/write accesses) and 32-bit data field (for
write accesses) must be specified. The address field specifies information for selecting the entry to
be accessed; the data field specifies the longword data to be written to the data array.
Specify the entry address for selecting the entry, the L bit indicating the longword position within
the (16-byte) line, and the W bit for selecting the way. In the L bit, B'00 is longword 0, B'01 is
longword 1, B'10 is longword 2, and B'11 is longword 3. In the W bit, B'00 is way 0, B'01 is way
1, B'10 is way 2, and B'11 is way 3. Since the access size of the data array is fixed at longword,
specify B'00 for bits 1 and 0 of the address.
For the address and data formats, see figure 7.4.
The following two operations are possible for the data array. Information in the address array is
not modified by this operation.
(1)
The data specified by the L bit in the address is read from the entry address specified by the
address and the entry corresponding to the way.
(2)
The longword data specified by the data is written to the position specified by the L bit in the
address from the entry address specified by the address and the entry corresponding to the way.
When writing with the associative bit (A bit) of the address field set to 1, the addresses in the four
Address-Array Write (Associative Operation)
Data Array Read
Data Array Write
Data Array
Rev. 2.00 Dec. 09, 2005 Page 195 of 1152
REJ09B0191-0200
Section 7 Cache