PIC18C242-I/SP Microchip Technology, PIC18C242-I/SP Datasheet - Page 158

• Manufacturer Part Number: PIC18C242-I/SP
• Description: IC MCU OTP 8KX16 A/D 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C242-I/SP

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 22
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Controller Family/series: PIC18
• No. Of I/o's: 23
• Ram Memory Size: 512Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: MSSP, SPI, I2C, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: ICE2000, DM163022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3DB18C452 - BOARD DAUGHTER ICEPIC3
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18CXX2
FIGURE 15-2:
FIGURE 15-3:
TABLE 15-6:
DS39026C-page 156
INTCON
PIR1
PIE1
IPR1
RCSTA
TXREG
TXSTA
SPBRG
Legend: x = unknown, - = unimplemented locations read as '0'.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits
TXIF bit
(interrupt reg. flag)
RC6/TX/CK (pin)
Note:
Name
TRMT bit
(Transmit shift
reg. empty flag)
Write to TXREG
RC6/TX/CK (pin)
Write to TXREG
TXIF bit
(Transmit buffer
reg. empty flag)
TRMT bit
(Transmit shift
reg. empty flag)
BRG Output
(shift clock)
BRG Output
(shift clock)
Shaded cells are not used for Asynchronous Transmission.
This timing diagram shows two consecutive transmissions.
clear.
USART Transmit Register
Baud Rate Generator Register
GIE/GIEH
PSPIF
PSPIE
PSPIP
CSRC
SPEN
Bit 7
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
(1)
(1)
(1)
ASYNCHRONOUS TRANSMISSION
ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
Transmit Shift Reg.
Word 1
PEIE/
ADIE
ADIP
Bit 6
GIEL
ADIF
RX9
TX9
Word 1
Word 1
Transmit Shift Reg
Word 1
TMR0IE INT0IE
SREN
TXEN
RCIF
RCIE
RCIP
Bit 5
START Bit
Word 2
START Bit
CREN ADDEN
SYNC
Bit 4
TXIF
TXIE
TXIP
Bit 0
Bit 0
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
RBIE
Bit 3
—
Bit 1
Word 1
TMR0IF INT0IF
BRGH
FERR
Bit 1
Bit 2
Word 1
OERR
TRMT
Bit 1
Bit 7/8
Word 2
Transmit Shift Reg.
RX9D
TX9D
RBIF
Bit 0
Bit 7/8
STOP Bit
2001 Microchip Technology Inc.
0000 000x 0000 000u
0000 -00x 0000 -00x
0000 0000 0000 0000
0000 -010 0000 -010
0000 0000 0000 0000
STOP Bit
Value on
POR,
BOR
START Bit
Word 2
Value on
RESETS
all other
Bit 0