PIC18C242-I/SP Microchip Technology, PIC18C242-I/SP Datasheet - Page 197

• Manufacturer Part Number: PIC18C242-I/SP
• Description: IC MCU OTP 8KX16 A/D 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C242-I/SP

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 22
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Controller Family/series: PIC18
• No. Of I/o's: 23
• Ram Memory Size: 512Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: MSSP, SPI, I2C, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: ICE2000, DM163022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3DB18C452 - BOARD DAUGHTER ICEPIC3
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ANDWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
2001 Microchip Technology Inc.
Before Instruction
After Instruction
Decode
REG
WREG
REG
Q1
WREG
=
=
=
=
register ’f’
AND WREG with f
[ label ] ANDWF
0
d
a
(WREG) .AND. (f)
N,Z
The contents of WREG are AND’ed
with register 'f'. If 'd' is 0, the result
is stored in WREG. If 'd' is 1, the
result is stored back in register 'f'
(default). If ‘a’ is 0, the Access
Bank will be selected. If ‘a’ is 1, the
BSR will not be overridden
(default).
1
1
ANDWF
Read
0001
Q2
0x17
0xC2
0x02
0xC2
f
[0,1]
[0,1]
255
01da
REG, 0, 0
Process
Data
Q3
ffff
f [,d [,a]
dest
destination
Write to
Q4
ffff
BC
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
PC
If Carry
If Carry
No
Q1
Q1
PC
PC
Read literal
Read literal
operation
Branch if Carry
[ label ] BC
-128
if carry bit is ’1’
None
If the Carry bit is ’1’, then the pro-
gram will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
1
1(2)
HERE
(PC) + 2 + 2n
1110
No
Q2
Q2
’n’
’n’
=
=
=
=
PIC18CXX2
n
address (HERE)
1;
address (HERE+12)
0;
address (HERE+2)
127
0010
operation
BC
Process
Process
Data
Data
n
No
Q3
Q3
DS39026C-page 195
5
PC
nnnn
Write to PC
operation
operation
No
No
Q4
Q4
nnnn