PIC18C242-I/SP Microchip Technology, PIC18C242-I/SP Datasheet - Page 221

• Manufacturer Part Number: PIC18C242-I/SP
• Description: IC MCU OTP 8KX16 A/D 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C242-I/SP

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 22
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Controller Family/series: PIC18
• No. Of I/o's: 23
• Ram Memory Size: 512Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: MSSP, SPI, I2C, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: ICE2000, DM163022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3DB18C452 - BOARD DAUGHTER ICEPIC3
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

RETURN
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
2001 Microchip Technology Inc.
After Interrupt
operation
Decode
No
PC
Q1
= TOS
operation
operation
Return from Subroutine
[ label ]
s
(TOS)
if s = 1
(WS)
(STATUSS)
(BSRS)
PCLATU, PCLATH are unchanged
None
Return from subroutine. The stack
is popped and the top of the stack
(TOS) is loaded into the program
counter. If ‘s’= 1, the contents of the
shadow registers WS, STATUSS
and BSRS are loaded into their cor-
responding registers, WREG,
STATUS and BSR. If ‘s’ = 0, no
update of these registers occurs
(default).
1
2
RETURN
0000
No
No
Q2
[0,1]
WREG,
PC,
RETURN [s]
0000
BSR,
operation
Process
Data
No
STATUS,
Q3
0001
pop PC from
operation
stack
No
Q4
001s
RLCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
C
REG
WREG
C
Q1
=
=
=
=
=
register ’f’
Rotate Left f through Carry
[ label ]
0
d
a
(f<n>)
(f<7>)
(C)
C,N,Z
The contents of register 'f' are
rotated one bit to the left through
the Carry Flag. If 'd' is 0, the result
is placed in WREG. If 'd' is 1, the
result is stored back in register 'f'
(default). If ‘a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ = 1, then the
bank will be selected as per the
BSR value (default).
1
1
RLCF
Read
Q2
0011
1110 0110
0
1110 0110
1100 1100
1
f
PIC18CXX2
[0,1]
[0,1]
C
dest<0>
255
dest<n+1>,
C,
RLCF
01da
Process
REG, 0, 0
Data
Q3
register f
DS39026C-page 219
f [,d [,a]
ffff
destination
Write to
Q4
ffff