PIC18C242-I/SP Microchip Technology, PIC18C242-I/SP Datasheet - Page 60

• Manufacturer Part Number: PIC18C242-I/SP
• Description: IC MCU OTP 8KX16 A/D 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C242-I/SP

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 22
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Controller Family/series: PIC18
• No. Of I/o's: 23
• Ram Memory Size: 512Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: MSSP, SPI, I2C, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: ICE2000, DM163022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3DB18C452 - BOARD DAUGHTER ICEPIC3
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18CXX2
FIGURE 5-3:
5.2.2.1
The long write is what actually programs words of data
into the internal memory. When a TBLWT to the MSB of
the write block occurs, instruction execution is halted.
During this time, programming voltage and the data
stored in internal latches is applied to program memory.
For a long write to occur:
1.
2.
3.
If the LWRT bit is clear, a short write will occur and pro-
gram memory will not be changed. If the TBLWT is not
to the MSB of the write block, then the programming
phase is not initiated.
Setting the LWRT bit enables long writes when the
MCLR pin is taken to V
is set, it can be cleared only by performing a POR or
MCLR Reset.
To ensure that the memory location has been well pro-
grammed, a minimum programming time is required.
The long write can be terminated after the program-
ming time has expired by a RESET or an interrupt.
Having only one interrupt source enabled to terminate
the long write ensures that no unintended interrupts will
prematurely terminate the long write.
DS39026C-page 58
MCLR/V
voltage
LWRT bit must be set
TBLWT to the address of the MSB of the write
block
PP
Operation
pin must be at the programming
HOLDING REGISTER AND THE WRITE BLOCK
PP
voltage. Once the LWRT bit
Program Memory (x 2-bits)
Block n
Block n + 1
Block n + 2
5.2.2.2
The sequence of events for programming an internal
program memory location should be:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. If GIE was set, service the interrupt request.
11. Lower MCLR/V
12. Verify the memory location (Table Read).
Enable the interrupt that terminates the long
write. Disable all other interrupts.
Clear the source interrupt flag.
If Interrupt Service Routine execution is desired
when
interrupts.
Set LWRT bit in the RCON register.
Raise MCLR/V
voltage, V
Clear the WDT (if enabled).
Set the interrupt source to interrupt at the
required time.
Execute the Table Write for the lower (even)
byte. This will be a short write.
Execute the Table Write for the upper (odd) byte.
This will be a long write. The microcontroller will
then halt internal operations. (This is not the
same as SLEEP mode, as the clocks and
peripherals will continue to run.) The interrupt
will cause the microcontroller to resume
operation.
MSB
The write to the MSB of the Write Block
causes the entire block to be written to pro-
gram memory. The program memory block
that is written depends on the address that is
written to in the MSB of the Write Block.
Write Block
the
Sequence of Events
PP
.
device
PP
PP
pin to V
pin to the programming
2001 Microchip Technology Inc.
Holding Register
wakes,
DD
.
enable
global