PIC18C242-I/SP Microchip Technology, PIC18C242-I/SP Datasheet - Page 223

• Manufacturer Part Number: PIC18C242-I/SP
• Description: IC MCU OTP 8KX16 A/D 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C242-I/SP

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 22
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Controller Family/series: PIC18
• No. Of I/o's: 23
• Ram Memory Size: 512Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: MSSP, SPI, I2C, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: ICE2000, DM163022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3DB18C452 - BOARD DAUGHTER ICEPIC3
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

RRNCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example 1:
Example 2:
Q Cycle Activity:
2001 Microchip Technology Inc.
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
REG
REG
WREG
REG
WREG
REG
Q1
=
=
=
=
=
=
register ’f’
Rotate Right f (no carry)
[ label ]
0
d
a
(f<n>)
(f<0>)
N,Z
The contents of register ’f’ are
rotated one bit to the right. If ’d’ is 0,
the result is placed in WREG. If ’d’
is 1, the result is placed back in
register 'f' (default). If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, then
the bank will be selected as per the
BSR value (default).
1
1
RRNCF
RRNCF
Read
0100
Q2
1101 0111
1110 1011
?
1101 0111
1110 1011
1101 0111
f
[0,1]
[0,1]
255
dest<n-1>,
dest<7>
REG, 1, 0
REG, 0, 0
RRNCF
00da
Process
Data
Q3
register f
ffff
f [,d [,a]
destination
Write to
Q4
ffff
SETF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
REG
Q1
register ’f’
Set f
[label] SETF
0
a
FFh
None
The contents of the specified regis-
ter are set to FFh. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, then
the bank will be selected as per the
BSR value (default).
1
1
SETF
Read
0110
Q2
=
=
f
[0,1]
PIC18CXX2
255
f
0x5A
0xFF
100a
Process
Data
f [,a]
REG,1
Q3
DS39026C-page 221
ffff
register ’f’
Write
Q4
ffff