PIC18C242-I/SP Microchip Technology, PIC18C242-I/SP Datasheet - Page 264

IC MCU OTP 8KX16 A/D 28DIP

PIC18C242-I/SP

Manufacturer Part Number
PIC18C242-I/SP
Description
IC MCU OTP 8KX16 A/D 28DIP
Manufacturer
Microchip Technology
Series
PIC® 18Cr

Specifications of PIC18C242-I/SP

Core Size
8-Bit
Program Memory Size
16KB (8K x 16)
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Number Of I /o
22
Program Memory Type
OTP
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
23
Ram Memory Size
512Byte
Cpu Speed
40MHz
No. Of Timers
4
Processor Series
PIC18C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
MSSP, SPI, I2C, USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
23
Number Of Timers
1 x 16 bit
Operating Supply Voltage
2.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
ICE2000, DM163022, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
5 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
I3DB18C452 - BOARD DAUGHTER ICEPIC3
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
PIC18CXX2
FIGURE 21-22:
TABLE 21-22: A/D CONVERSION REQUIREMENTS
DS39026C-page 262
Param
130
131
132
135
136
Note 1: ADRES register may be read on the following T
No.
A/D DATA
2: See Section 16.0 for minimum conditions, when input voltage has changed more than 1 LSb.
3: The time for the holding capacitor to acquire the “New” input voltage, when the voltage changes full scale
4: On the next Q4 cycle of the device clock.
5: The time of the A/D clock period is dependent on the device frequency and the T
Note 1: If the A/D clock source is selected as RC, a time of T
SAMPLE
A/D CLK
ADRES
T
T
T
T
T
Symbol
BSF ADCON0, GO
AD
CNV
ACQ
SWC
AMP
after the conversion (AV
50 .
ADIF
GO
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
Q4
This allows the SLEEP instruction to be executed.
A/D clock period
Conversion time
(not including acquisition time) (Note 1)
Acquisition time (Note 3)
Switching Time from convert
Amplifier settling time (Note 2)
132
A/D CONVERSION TIMING
Note 2
Characteristic
DD
9
to AV
PIC18CXXX
PIC18LCXXX
PIC18CXXX
PIC18LCXXX
SS
8
, or AV
OLD_DATA
7
sample
SS
to AV
. . .
SAMPLING STOPPED
CY
CY
is added before the A/D clock starts.
DD
cycle.
. . .
131
130
). The source impedance (R
Min
1.6
3.0
2.0
3.0
11
15
10
1
2
(Note 4)
20
20
Max
6.0
9.0
12
(5)
(5)
1
Units
T
AD
s
s
s
s
s
s
s
0
T
T
A/D RC mode
A/D RC mode
-40 C
This may be used if the
“new” input voltage has not
changed by more than 1 LSb
(i.e., 5 mV @ 5.12V) from
the last sampled voltage (as
stated on C
2001 Microchip Technology Inc.
OSC
OSC
0 C
S
AD
) on the input channels is
based, V
based, V
clock divider.
NEW_DATA
DONE
Temp
Temp
Conditions
HOLD
T
REF
REF
CY
125 C
125 C
).
full range
3.0V

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