PIC18C242-I/SP Microchip Technology, PIC18C242-I/SP Datasheet - Page 208

• Manufacturer Part Number: PIC18C242-I/SP
• Description: IC MCU OTP 8KX16 A/D 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C242-I/SP

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 22
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Controller Family/series: PIC18
• No. Of I/o's: 23
• Ram Memory Size: 512Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: MSSP, SPI, I2C, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: ICE2000, DM163022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3DB18C452 - BOARD DAUGHTER ICEPIC3
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18CXX2
DAW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example1:
Example 2:
DS39026C-page 206
Q Cycle Activity:
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
WREG
C
DC
WREG
C
DC
WREG
C
DC
WREG
C
DC
Q1
=
=
=
=
=
=
=
=
=
=
=
=
Decimal Adjust WREG Register
[label] DAW
None
If [WREG<3:0> >9] or [DC = 1] then
(WREG<3:0>) + 6
else
(
If [WREG<7:4> >9] or [C = 1] then
(
else
(WREG<7:4>)
C
DAW adjusts the eight-bit value in
WREG, resulting from the earlier
addition of two variables (each in
packed BCD format) and produces
a correct packed BCD result.
1
1
DAW
register
WREG
WREG<3:0>)
WREG<7:4>) + 6
Read
0000
Q2
0xA5
0
0
0x05
1
0
0xCE
0
0
0x34
1
0
0000
Process
Data
Q3
WREG<7:4>;
WREG<3:0>;
0000
WREG<3:0>;
WREG<7:4>;
WREG
Write
Q4
0111
DECF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
CNT
Z
CNT
Z
Q1
=
=
=
=
register ’f’
Decrement f
[ label ] DECF f [,d [,a]
0
d
a
(f) – 1
C,DC,N,OV,Z
Decrement register 'f'. If 'd' is 0, the
result is stored in WREG. If 'd' is 1,
the result is stored back in register
'f' (default). If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ = 1, then the
bank will be selected as per the
BSR value (default).
1
1
DECF
Read
0000
Q2
0x01
0
0x00
1
f
[0,1]
[0,1]
2001 Microchip Technology Inc.
255
dest
CNT,
01da
Process
Data
Q3
1, 0
ffff
destination
Write to
Q4
ffff