PIC18C242-I/SP Microchip Technology, PIC18C242-I/SP Datasheet - Page 206

• Manufacturer Part Number: PIC18C242-I/SP
• Description: IC MCU OTP 8KX16 A/D 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C242-I/SP

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 22
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Controller Family/series: PIC18
• No. Of I/o's: 23
• Ram Memory Size: 512Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: MSSP, SPI, I2C, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: ICE2000, DM163022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3DB18C452 - BOARD DAUGHTER ICEPIC3
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18CXX2
COMF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39026C-page 204
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
REG
WREG
Q1
=
=
=
register ’f’
Complement f
[ label ] COMF
0
d
a
N,Z
The contents of register ’f’ are com-
plemented. If ’d’ is 0, the result is
stored in WREG. If ’d’ is 1, the
result is stored back in register ’f’
(default). If ‘a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
1
1
COMF
( f )
Read
0001
Q2
0x13
0x13
0xEC
f
[0,1]
[0,1]
255
dest
11da
REG, 0, 0
Process
Data
Q3
f [,d [,a]
ffff
destination
Write to
Q4
ffff
CPFSEQ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC Address =
WREG
REG
If REG
If REG
No
No
No
Q1
Q1
Q1
PC
PC
register ’f’
operation
operation
operation
Compare f with WREG,
skip if f = WREG
[ label ] CPFSEQ
0
a
(f) – (WREG),
skip if (f) = (WREG)
(unsigned comparison)
None
Compares the contents of data
memory location 'f' to the contents
of WREG by performing an
unsigned subtraction.
If 'f' = WREG
instruction is discarded and a NOP
is executed instead, making this a
two-cycle instruction. If ‘a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
1
1(2)
Note: 3 cycles if skip and followed
HERE
NEQUAL
EQUAL
Read
0110
Q2
No
No
No
Q2
Q2
=
=
=
=
=
f
[0,1]
2001 Microchip Technology Inc.
255
by a 2-word instruction.
HERE
?
?
WREG;
Address (EQUAL)
WREG;
Address (NEQUAL)
CPFSEQ REG, 0
:
:
001a
operation
operation
operation
Process
,
Data
then the fetched
No
No
No
Q3
Q3
Q3
ffff
f [,a]
operation
operation
operation
operation
Q4
No
No
No
No
Q4
Q4
ffff