PIC18C242-I/SP Microchip Technology, PIC18C242-I/SP Datasheet - Page 216

• Manufacturer Part Number: PIC18C242-I/SP
• Description: IC MCU OTP 8KX16 A/D 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C242-I/SP

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 22
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Controller Family/series: PIC18
• No. Of I/o's: 23
• Ram Memory Size: 512Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: MSSP, SPI, I2C, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: ICE2000, DM163022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3DB18C452 - BOARD DAUGHTER ICEPIC3
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18CXX2
MULLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39026C-page 214
Q Cycle Activity:
Before Instruction
After Instruction
Decode
WREG
PRODH
PRODL
WREG
PRODH
PRODL
Q1
literal ’k’
Multiply Literal with WREG
[ label ]
0
(WREG) x k
None
An unsigned multiplication is car-
ried out between the contents of
WREG and the 8-bit literal ’k’.
The 16-bit result is placed in
PRODH:PRODL register pair.
PRODH contains the high byte.
WREG is unchanged.
None of the status flags are
affected.
Note that neither overflow, nor
carry is possible in this opera-
tion. A zero result is possible but
not detected.
1
1
MULLW
Read
0000
Q2
=
=
=
=
=
=
k
255
0xE2
?
?
0xE2
0xAD
0x08
0xC4
MULLW
1101
Process
Data
Q3
PRODH:PRODL
kkkk
k
PRODH:
registers
PRODL
Write
Q4
kkkk
MULWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
WREG
REG
PRODH
PRODL
WREG
REG
PRODH
PRODL
Q1
register ’f’
Multiply WREG with f
[ label ]
0
a
(WREG) x (f)
None
An unsigned multiplication is car-
ried out between the contents of
WREG and the register file loca-
tion ’f’. The 16-bit result is stored
in the PRODH:PRODL register
pair. PRODH contains the high
byte.
Both WREG and ’f’ are
unchanged.
None of the status flags are
affected.
Note that neither overflow, nor
carry is possible in this opera-
tion. A zero result is possible but
not detected. If ‘a’ is 0, the
Access Bank will be selected,
overriding the BSR value. If ‘a’=
1, then the bank will be selected
as per the BSR value (default).
1
1
MULWF
Read
0000
Q2
=
=
=
=
=
=
=
=
f
[0,1]
2001 Microchip Technology Inc.
255
0xC4
0xB5
?
?
0xC4
0xB5
0x8A
0x94
REG, 1
MULWF
001a
Process
Data
Q3
PRODH:PRODL
ffff
f [,a]
PRODH:
registers
PRODL
Write
Q4
ffff