MC68HC908JB8JPE Freescale Semiconductor, MC68HC908JB8JPE Datasheet - Page 11

• Manufacturer Part Number: MC68HC908JB8JPE
• Description: IC MCU FLASH 8BIT 8K 20-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908JB8JPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: USB
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Controller Family/series: HC08
• No. Of I/o's: 13
• Ram Memory Size: 256Byte
• Cpu Speed: 3MHz
• No. Of Timers: 1
• Embedded Interface Type: USB
• Rohs Compliant: Yes
• Processor Series: HC08JB
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: USB
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 2
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
8.8.1
8.8.2
8.8.3
9.1
9.2
9.3
9.4
9.5
9.5.1
9.5.1.1
9.5.1.2
9.5.1.3
9.5.1.4
9.5.1.5
9.5.1.6
9.5.2
9.5.3
9.5.4
9.5.4.1
9.5.4.2
9.5.4.3
9.5.5
9.6
9.7
9.7.1
9.7.2
9.7.2.1
9.7.2.2
9.7.2.3
9.7.2.4
9.7.2.5
9.7.3
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Section 9. Universal Serial Bus Module (USB)
Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . .116
USB Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Reset Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Resume After Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Low-Speed Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Voltage Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
USB Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
USB Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Sync Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Packet Identifier Field . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Address Field (ADDR) . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Endpoint Field (ENDP). . . . . . . . . . . . . . . . . . . . . . . . . . 128
Cyclic Redundancy Check (CRC) . . . . . . . . . . . . . . . . . 128
End-of-Packet (EOP) . . . . . . . . . . . . . . . . . . . . . . . . . . .128
Host Initiated Resume . . . . . . . . . . . . . . . . . . . . . . . . . . 131
USB Reset Signalling. . . . . . . . . . . . . . . . . . . . . . . . . . .131
Remote Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
Output Driver Characteristics . . . . . . . . . . . . . . . . . . . . . 134
Low Speed (1.5 Mbps) Driver Characteristics . . . . . . . . 134
Receiver Data Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Data Source Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Data Signal Rise and Fall Time . . . . . . . . . . . . . . . . . . . 136
Table of Contents
Table of Contents
Technical Data
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