MC68HC908JB8JPE Freescale Semiconductor, MC68HC908JB8JPE Datasheet - Page 246

IC MCU FLASH 8BIT 8K 20-DIP

MC68HC908JB8JPE

Manufacturer Part Number
MC68HC908JB8JPE
Description
IC MCU FLASH 8BIT 8K 20-DIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68HC908JB8JPE

Core Processor
HC08
Core Size
8-Bit
Speed
3MHz
Connectivity
USB
Peripherals
LVD, POR, PWM
Number Of I /o
13
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
20-DIP (0.300", 7.62mm)
Controller Family/series
HC08
No. Of I/o's
13
Ram Memory Size
256Byte
Cpu Speed
3MHz
No. Of Timers
1
Embedded Interface Type
USB
Rohs Compliant
Yes
Processor Series
HC08JB
Core
HC08
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
USB
Maximum Clock Frequency
3 MHz
Number Of Programmable I/os
37
Number Of Timers
2
Operating Supply Voltage
4 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details
Break Module (BREAK)
17.3 Features
17.4 Functional Description
Technical Data
246
Features of the break module include the following:
When the internal address bus matches the value written in the break
address registers, the break module issues a breakpoint signal (BKPT)
to the SIM. The SIM then causes the CPU to load the instruction register
with a software interrupt instruction (SWI) after completion of the current
CPU instruction. The program counter vectors to $FFFC and $FFFD
($FEFC and $FEFD in monitor mode).
These events can cause a break interrupt to occur:
When a CPU-generated address matches the contents of the break
address registers, the break interrupt begins after the CPU completes its
current instruction. A return-from-interrupt instruction (RTI) in the break
routine ends the break interrupt and returns the MCU to normal
operation.
Accessible i/o registers during the break interrupt
CPU-generated break interrupts
Software-generated break interrupts
COP disabling during break interrupts
A CPU-generated address (the address in the program counter)
matches the contents of the break address registers.
Software writes a logic 1 to the BRKA bit in the break status and
control register.
Figure 17-1
Break Module (BREAK)
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
shows the structure of the break module.
Freescale Semiconductor

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