MC68HC908JB8JPE Freescale Semiconductor, MC68HC908JB8JPE Datasheet - Page 21

• Manufacturer Part Number: MC68HC908JB8JPE
• Description: IC MCU FLASH 8BIT 8K 20-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908JB8JPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: USB
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Controller Family/series: HC08
• No. Of I/o's: 13
• Ram Memory Size: 256Byte
• Cpu Speed: 3MHz
• No. Of Timers: 1
• Embedded Interface Type: USB
• Rohs Compliant: Yes
• Processor Series: HC08JB
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: USB
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 2
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Figure
9-19 USB Control Register 0 (UCR0) . . . . . . . . . . . . . . . . . . . . . . . 145
9-20 USB Control Register 1 (UCR1) . . . . . . . . . . . . . . . . . . . . . . . 146
9-21 USB Control Register 2 (UCR2) . . . . . . . . . . . . . . . . . . . . . . . 147
9-22 USB Control Register 3 (UCR3) . . . . . . . . . . . . . . . . . . . . . . . 149
9-23 USB Control Register 4 (UCR4) . . . . . . . . . . . . . . . . . . . . . . . 151
9-24 USB Status Register 0 (USR0). . . . . . . . . . . . . . . . . . . . . . . . 152
9-25 USB Status Register 1 (USR1). . . . . . . . . . . . . . . . . . . . . . . . 153
9-26 USB Endpoint 0 Data Registers (UE0D0–UE0D7). . . . . . . . . 154
9-27 USB Endpoint 1 Data Registers (UE1D0–UE1D7). . . . . . . . . 155
9-28 USB Endpoint 2 Data Registers (UE2D0–UE2D7). . . . . . . . . 156
9-29 OUT Token Data Flow for Receive Endpoint 0. . . . . . . . . . . . 158
9-30 SETUP Token Data Flow for Receive Endpoint 0 . . . . . . . . . 159
9-31 IN Token Data Flow for Transmit Endpoint 0 . . . . . . . . . . . . . 160
9-32 IN Token Data Flow for Transmit Endpoint 1 . . . . . . . . . . . . . 161
10-1 Monitor Mode Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
10-2 Low-Voltage Monitor Mode Entry Flowchart. . . . . . . . . . . . . . 168
10-3 Monitor Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
10-4 Sample Monitor Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 170
10-5 Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
10-6 Break Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
10-7 Monitor Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .175
11-1 TIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
11-2 TIM I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .180
11-3 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . 184
11-4 TIM Status and Control Register (TSC) . . . . . . . . . . . . . . . . . 190
11-5 TIM Counter Registers (TCNTH:TCNTL) . . . . . . . . . . . . . . . . 192
11-6 TIM Counter Modulo Registers (TMODH:TMODL). . . . . . . . . 193
11-7 TIM Channel Status and Control Registers (TSC0:TSC1) . . . 194
11-8 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
11-9 TIM Channel Registers (TCH0H/L:TCH1H/L). . . . . . . . . . . . . 198
12-1 I/O Port Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .200
12-2 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . . 202
12-3 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . . 203
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