MC68HC908JB8JPE Freescale Semiconductor, MC68HC908JB8JPE Datasheet - Page 115

• Manufacturer Part Number: MC68HC908JB8JPE
• Description: IC MCU FLASH 8BIT 8K 20-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908JB8JPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: USB
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Controller Family/series: HC08
• No. Of I/o's: 13
• Ram Memory Size: 256Byte
• Cpu Speed: 3MHz
• No. Of Timers: 1
• Embedded Interface Type: USB
• Rohs Compliant: Yes
• Processor Series: HC08JB
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: USB
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 2
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Address:
POR — Power-On Reset Bit
PIN — External Reset Bit
COP — Computer Operating Properly Reset Bit
ILOP — Illegal Opcode Reset Bit
ILAD — Illegal Address Reset Bit (opcode fetches only)
USB — Universal Serial Bus Reset Bit
LVI — Low voltage inhibit Reset Bit
Read:
Write:
POR:
An illegal opcode reset has occurred since the last read of the RSR
1 = A POR has occurred
0 = Read of RSR
1 = An external reset has occurred since the last read of the RSR
0 = Read of RSR
1 = A COP reset has occurred since the last read of the RSR
0 = POR or read of RSR
0 = POR or read of RSR
1 = An illegal address reset has occurred since the last read of the
0 = POR or read of RSR
1 = Last reset caused by the USB module
0 = POR or read of RSR
1 = A LVI reset has occurred since the last read of PSR
0 = POR or read of RSR
$FE01
POR
Bit 7
RSR
1
System Integration Module (SIM)
Figure 8-19. Reset Status Register (RSR)
= Unimplemented
PIN
6
0
COP
0
5
ILOP
0
4
ILAD
3
0
System Integration Module (SIM)
USB
2
0
LVI
1
0
Technical Data
SIM Registers
Bit 0
0
0
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