M37544G2AGP#U0 Renesas Electronics America, M37544G2AGP#U0 Datasheet - Page 22

• Manufacturer Part Number: M37544G2AGP#U0
• Description: IC 740 MCU OTP 8K 32LQFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M37544G2AGP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SIO, UART/USART
• Peripherals: WDT
• Number Of I /o: 25
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: QzROM
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

REJ03B0108-0103
page 20 of 72
7544 Group (QzROM version)
Interrupts
The 7544 Group interrupts are vector interrupts with a fixed prior-
ity scheme, and generated by 12 sources: 5 external, 6 internal,
and 1 software.
The interrupt sources, vector addresses
are shown in Table 8.
Each interrupt except the BRK instruction interrupt has the inter-
rupt request bit and the interrupt enable bit. These bits and the
interrupt disable flag (I flag) control the acceptance of interrupt re-
quests. Fig. 17 shows an interrupt control diagram.
Table 8 Interrupt vector addresses and priority
Note 1: Vector addressed contain internal jump destination addresses.
Reset (Note 2)
Serial I/O receive
Serial I/O transmit
INT
INT
Key-on wake-up
CNTR
CNTR
Timer X
Reserved area
Reserved area
Timer A
Reserved area
A/D conversion
Timer 1
Reserved area
BRK instruction
Interrupt source
0
1
2: Reset function in the same way as an interrupt with the highest priority.
0
1
Priority
10
11
12
13
—
—
—
—
1
2
3
4
5
6
7
8
9
Rev.1.03
Vector addresses (Note 1)
High-order
FFFD
FFED
FFEB
FFDF
FFDD
FFFB
FFF9
FFF7
FFF5
FFF3
FFEF
FFE9
FFE7
FFE5
FFE3
FFE1
FFF1
16
16
16
16
16
16
16
16
16
16
Mar 31, 2009
16
16
16
16
16
16
16
(1)
Low-order
, and interrupt priority
FFDC
FFFC
FFEE
FFEC
FFEA
FFDE
FFFA
FFF8
FFF6
FFF4
FFF2
FFF0
FFE8
FFE6
FFE4
FFE2
FFE0
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
At reset input
At completion of serial I/O data receive
At completion of serial I/O transmit shift or
when transmit buffer is empty
At detection of either rising or falling edge of
INT
At detection of either rising or falling edge of
INT
At falling of conjunction of input logical level
for port P0 (at input)
At detection of either rising or falling edge of
CNTR
At detection of either rising or falling edge of
CNTR
At timer X underflow
Not available
Not available
At timer A underflow
Not available
At completion of A/D conversion
At timer 1 underflow
Not available
At BRK instruction execution
Interrupt request generating conditions
0
1
input
input
0
1
input
input
An interrupt request is accepted when all of the following condi-
tions are satisfied:
Though the interrupt priority is determined by hardware, priority
processing can be performed by software using the above bits
and flag.
• Interrupt disable flag.................................“0”
• Interrupt request bit...................................“1”
• Interrupt enable bit....................................“1”
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt (valid at falling)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
STP release timer underflow
Non-maskable software interrupt
Remarks