M37544G2AGP#U0 Renesas Electronics America, M37544G2AGP#U0 Datasheet - Page 43

• Manufacturer Part Number: M37544G2AGP#U0
• Description: IC 740 MCU OTP 8K 32LQFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M37544G2AGP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SIO, UART/USART
• Peripherals: WDT
• Number Of I /o: 25
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: QzROM
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

REJ03B0108-0103
page 41 of 72
7544 Group (QzROM version)
(1) Oscillation control
• Stop mode
When the STP instruction is executed, the internal clock φ stops at
an “H” level and the X
to “01
bilization time set bit after release of the STP instruction is “0”. On
the other hand, timer 1 and prescaler 1 are not set when the
above bit is “1”. Accordingly, set the wait time fit for the oscillation
stabilization time of the oscillator to be used. Single selected by
the timer 1 count source selection bit is connected to the input of
prescaler 1. When an external interrupt is accepted, oscillation is
restarted but the internal clock φ remains at “H” until timer 1
underflows. As soon as timer 1 underflows, the internal clock φ is
supplied. This is because when a ceramic/quartz-crystal oscillator
is used, some time is required until a start of oscillation. In case
oscillation is restarted by reset, no wait time is generated. So ap-
ply an “L” level to the RESET pin while oscillation becomes stable.
Also, the STP instruction cannot be used while CPU is operating
by an on-chip oscillator.
• Wait mode
If the WIT instruction is executed, the internal clock φ stops at an
“H” level, but the oscillator does not stop. The internal clock re-
starts if a reset occurs or when an interrupt is received. Since the
oscillator does not stop, normal operation can be started immedi-
ately after the clock is restarted. To ensure that interrupts will be
received to release the STP or WIT state, interrupt enable bits
must be set to “1” before the STP or WIT instruction is executed.
For use with the oscillation stabilization set bit after release of the
STP instruction set to “1”, set values in timer 1 and prescaler 1 af-
ter fully appreciating the oscillation stabilization time of the
oscillator to be used.
• Switch of ceramic/quartz-crystal and RC oscillations
After releasing reset the operation starts by starting an on-chip os-
cillator. Then, a ceramic/quartz-crystal oscillation or an RC
oscillation is selected by setting bit 5 of the CPU mode register.
• Double-speed mode
When a ceramic/quartz-crystal oscillation is selected, a double-
speed mode can be used. Do not use it when an RC oscillation is
selected.
• CPU mode register
Bits 5, 1 and 0 of CPU mode register are used to select oscillation
mode and to control operation modes of the microcomputer. In or-
der to prevent the dead-lock by error-writing (ex. program
run-away), these bits can be rewritten only once after releasing re-
set. After rewriting it is disable to write any data to the bit. (The
emulator MCU “M37544RSS” is excluded.)
Also, when the read-modify-write instructions (SEB, CLB) are ex-
ecuted to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked.
Notes on clock generating circuit
16
” and prescaler 1 is set to “FF
______
IN
Rev.1.03
oscillator stops. At this time, timer 1 is set
Mar 31, 2009
16
” when the oscillation sta-
• Clock division ratio, X
trol
The state transition shown in Fig. 49 can be performed by setting
the clock division ratio selection bits (bits 7 and 6), X
control bit (bit 4), on-chip oscillator oscillation control bit (bit 3) of
CPU mode register. Be careful of notes on use in Fig. 49.
• Count source (Timer 1, Timer A, Timer X, Serial I/O, A/D con-
verter, Watchdog timer)
The count sources of these functions are affected by the clock di-
vision selection bit of the CPU mode register.
The f(X
f(X
The on-chip oscillator output is supplied to these functions when
selecting the on-chip oscillator output as the CPU clock.
Fig. 45 Structure of CPU mode register
b7
IN
Note 1: The bit can be rewritten only once after releasing reset. After rewriting
) as the CPU clock.
2: These bits are used only when a ceramic
IN
) clock is supplied to the watchdog timer when selecting
Do not use these when an RC oscillation is selected.
it is disable to write any data to the bit. However, by reset the bit is
initialized and can be rewritten, again.
(It is not disable to write any data to the bit for emulator MCU
“M37544RSS”.)
IN
b0
oscillation control, on-chip oscillator con-
CPU mode register
(CPUM: address 003B
Processor mode bits (Note 1)
Stack page selection bit
On-chip oscillator oscillation control bit
X
Oscillation mode selection bit (Note 1)
Clock division ratio selection bits
IN
b1 b0
b7 b6
0
0
1
1
0 : 0 page
1 : 1 page
0 : On-chip oscillator oscillation enabled
1 : On-chip oscillator oscillation stop
0 : Ceramic/quartz-crystal or RC oscillation enabled
1 : Ceramic/quartz-crystal or RC oscillation stop
0 : Ceramic/quartz-crystal oscillation
1 : RC oscillation
0
0
1
1
oscillation control bit
0 Single-chip mode
1
0
1
0 : f(φ) = f(X
1 : f(φ) = f(X
0 : applied from on-chip oscillator
1 : f(φ) = f(X
Not available
/quartz-crystal
16
IN
IN
IN
, initial value: 80
)/2 (High-speed mode)
)/8 (Middle-speed mode)
) (Double-speed mode)(Note 2)
oscillation is selected.
16
)
IN
oscillation