M37544G2AGP#U0 Renesas Electronics America, M37544G2AGP#U0 Datasheet - Page 25

• Manufacturer Part Number: M37544G2AGP#U0
• Description: IC 740 MCU OTP 8K 32LQFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M37544G2AGP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SIO, UART/USART
• Peripherals: WDT
• Number Of I /o: 25
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: QzROM
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

REJ03B0108-0103
page 23 of 72
7544 Group (QzROM version)
• Interrupt Request Generation, Acceptance, and Handling
Interrupts have the following three phases.
(i) Interrupt Request Generation
(ii) Interrupt Request Acceptance
(iii) Handling of Accepted Interrupt Request
Fig. 19 shows the time up to execution in the interrupt processing
routine, and Fig. 20 shows the interrupt sequence.
Fig. 21 shows the timing of interrupt request generation, interrupt
request bit, and interrupt request acceptance.
Fig. 19 Time up to execution in interrupt routine
An interrupt request is generated by an interrupt source (ex-
ternal interrupt signal input, timer underflow, etc.) and the
corresponding request bit is set to “1”.
Based on the interrupt acceptance timing in each instruction
cycle, the interrupt control circuit determines acceptance con-
ditions (interrupt request bit, interrupt enable bit, and interrupt
disable flag) and interrupt priority levels for accepting interrupt
requests. When two or more interrupt requests are generated
simultaneously, the highest priority interrupt is accepted. The
value of the interrupt request bit for an unaccepted interrupt
remains the same and acceptance is determined at the next
interrupt acceptance timing point.
The accepted interrupt request is processed.
Interrupt request
Rev.1.03
generated
Main routine
* When executing DIV instruction
0 to 16* cycles
Mar 31, 2009
Interrupt request
acceptance
7 to 23 cycles
Interrupt sequence
Vector fetch
Stack push
7 cycles
• Interrupt Handling Execution
When interrupt handling is executed, the following operations are
performed automatically.
(1) Once the currently executing instruction is completed, an in-
(2) The contents of the program counters and the processor sta-
(3) Concurrently with the push operation, the jump address of the
(4) The interrupt request bit for the corresponding interrupt is set
(5) The interrupt routine is executed.
(6) When the RTI instruction is executed, the contents of the reg-
As described above, it is necessary to set the stack pointer and
the jump address in the vector area corresponding to each inter-
rupt to execute the interrupt processing routine.
terrupt request is accepted.
tus register at this point are pushed onto the stack area in
order from 1 to 3.
1.High-order bits of program counter (PCH)
2.Low-order bits of program counter (PCL)
3.Processor status register (PS)
corresponding interrupt (the start address of the interrupt pro-
cessing routine) is transferred from the interrupt vector to the
program counter.
to “0”. Also, the interrupt disable flag is set to “1” and multiple
interrupts are disabled.
isters pushed onto the stack area are popped off in the order
from 3 to 1. Then, the routine that was before running interrupt
processing resumes.
Interrupt routine
starts
Interrupt handling
routine