M37544G2AGP#U0 Renesas Electronics America, M37544G2AGP#U0 Datasheet - Page 38

• Manufacturer Part Number: M37544G2AGP#U0
• Description: IC 740 MCU OTP 8K 32LQFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M37544G2AGP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SIO, UART/USART
• Peripherals: WDT
• Number Of I /o: 25
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: QzROM
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

REJ03B0108-0103
page 36 of 72
7544 Group (QzROM version)
Watchdog Timer
The watchdog timer gives a means for returning to a reset status
when the program fails to run on its normal loop due to a runaway.
The watchdog timer consists of an 8-bit watchdog timer H and an
8-bit watchdog timer L, being a 16-bit counter.
Standard operation of watchdog timer
The watchdog timer stops when the watchdog timer control regis-
ter (address 0039
value to the watchdog timer control register (address 0039
causes the watchdog timer to start to count down. When the
watchdog timer H underflows, an internal reset occurs. Accord-
ingly, it is programmed that the watchdog timer control register
(address 0039
When the watchdog timer control register (address 0039
read, the values of the high-order 6-bit of the watchdog timer H,
STP instruction function selection bit and watchdog timer H count
source selection bit are read.
Initial value of watchdog timer
By a reset or writing to the watchdog timer control register (ad-
dress 0039
watchdog timer L is set to “FF
Operation of watchdog timer H count source selection bit
A watchdog timer H count source can be selected by bit 7 of the
watchdog timer control register (address 0039
“0”, the count source becomes a watchdog timer L underflow sig-
nal. The detection time is 131.072 ms at f(X
When this bit is “1”, the count source becomes f(X
oscillator/16. In this case, the detection time is 512 µs at f(X
MHz.
This bit is cleared to “0” after reset.
16
), the watchdog timer H is set to “FF
16
) can be set before an underflow occurs.
16
) is not set after reset. Writing an optional
Rev.1.03
16
”.
Mar 31, 2009
IN
)=8 MHz.
16
). When this bit is
IN
)/16 or on-chip
16
” and the
16
IN
) is
)=8
16
)
Operation of STP instruction function selection bit
The function of the STP instruction can be set by the STP instruc-
tion function selection bit (bit 6 of WDTCON).
When “0” is set to this bit, system enters into the stop mode at the
STP instruction execution.
When “1” is set to this bit, internal reset occurs at the STP instruc-
tion execution.
Once this bit is set to “1”, it cannot be changed to “0” by program.
This bit is cleared to “0” after reset.
1. The watchdog timer is operating during the wait mode. Write
2. The watchdog timer stops during the stop mode. However, the
3. The STP instruction function selection bit (bit 6 of watchdog
Notes on watchdog timer
data to the watchdog timer control register to prevent timer un-
derflow.
watchdog timer is running during the oscillation stabilizing time
after the STP instruction is released. In order to avoid the un-
derflow of the watchdog timer, the watchdog timer count source
selection bit (bit 7 of watchdog timer control register (address
0039
timer control register (address 0039
once after releasing reset. After rewriting it is disable to write
any data to this bit.
16
)) before executing the STP instruction.
16
)) can be rewritten only