M37544G2AGP#U0 Renesas Electronics America, M37544G2AGP#U0 Datasheet - Page 75

• Manufacturer Part Number: M37544G2AGP#U0
• Description: IC 740 MCU OTP 8K 32LQFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M37544G2AGP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SIO, UART/USART
• Peripherals: WDT
• Number Of I /o: 25
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: QzROM
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.
1.00 Oct 26, 2004
1.01 Nov 24, 2004
1.02 Jul 20, 2005 All pages Delete the following: "PRELIMINARY".
1.03 Mar 31, 2009
Date
REVISION HISTORY
36, 70, 71 Operation of STP instruction disable bit
2, 4, 5, 7 Package names are revised.
48-50
20-25
45-49
Page
3,8
46
12
18
41
45
53
61
13
17
18
19
36
37
41
50
51
54
55
65
66
70
–
3
7
First edition issued
Table 12 Electrical characteristics: Minimum value of V
The followings are added;
- A/D Converter characteristics
- Timing requirements
- Switching Characteristics
- Timing chart
Table 1 Performance overview is added.
Table 2 is deleted.
ROM code protect is added.
Fig.10 is partly revised.
Termination of unused pins is added.
(4)Wiring to CNV
(4)Wiring to V
Fig.49 is partly revised.
Table 8 is partly revised.
PACKAGE OUTLINE is revised.
Product shipped in blank, NOTES ON QzROM, DATA REQUIRED FOR QzROM
WRITING ORDERS are added.
42S1M package added
Fig. 11 Memory map diagram revised
Fig. 15 (5)Port P1
Fig. 16 (8)Port P1
Table 7 X
“Interrupts” revised
→ Operation of STP instruction function selection bit
Watchdog Timer
-Fig. 36 Block diagram of watchdog timer revised
-Fig. 37 Structure of watchdog timer control register revised
“-Clock division ratio, X
“QzROM Writing Mode”added
“Processor Status Register”revised
Fig. 57 V
5. Setup for I/O ports “Note” deleted
“NOTES ON QzROM” added
-“1. Processor Status Register”revised
APPENDIX “Fig. 2 Sequence of PLP Instruction execution deleted.
-Figure title of Fig. 3 revised
“3. Modifying output data with bit managing instruction” revised
Notes on A/D conversion 1. Analog input pin revised
Notes on Watchdog Timer revised
“Operation of watchdog timer H count source selection bit” revised
“Operation of STP instruction function selection bit” revised
“Notes on watchdog timer” added
PP
IN
, X
→ CNV
PP
OUT
pin is revised.
SS
1
4
added
revised
SS
revised
pin is deleted.
(1/2)
IN
7544 Group (QzROM version) Data Sheet
oscillation control, on-chip oscillator control” added
Description
Summary
RAM
revised.