M37544G2AGP#U0 Renesas Electronics America, M37544G2AGP#U0 Datasheet - Page 73

• Manufacturer Part Number: M37544G2AGP#U0
• Description: IC 740 MCU OTP 8K 32LQFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M37544G2AGP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SIO, UART/USART
• Peripherals: WDT
• Number Of I /o: 25
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: QzROM
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

REJ03B0108-0103
page 71 of 72
7544 Group (QzROM version)
Notes on Clock Generating Circuit
1. Switch of ceramic/quartz-crystal oscillation and RC oscillation
After releasing reset, the oscillation mode selection bit (bit 5 of
CPU mode register (address 003B
tal oscillation selected). When the RC oscillation is used, after
releasing reset, set this bit to “1”.
2. Double-speed mode
The double-speed mode can be used only when a ceramic oscilla-
tion is selected. Do not use it when an RC oscillation is selected.
3. CPU mode register
Oscillation mode selection bit (bit 5), processor mode bits (bits 1
and 0) of CPU mode register (address 003B
oscillation mode and to control operation modes of the microcom-
puter. In order to prevent the dead-lock by erroneously writing (ex.
program run-away), these bits can be rewritten only once after re-
leasing reset. After rewriting, it is disabled to write any data to the
bit. (The emulator MCU “M37542RSS” is excluded.)
Also, when the read-modify-write instructions (SEB, CLB, etc.) are
executed to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked.
4. Clock division ratio, X
control
The state transition shown in Fig. 49 can be performed by setting
the clock division ratio selection bits (bits 7 and 6), X
control bit (bit 4), on-chip oscillator oscillation control bit (bit 3) of
CPU mode register. Be careful of notes on use in Fig. 49.
5. On-chip oscillator operation
When the MCU operates by the on-chip oscillator for the main
clock, connect X
leave X
The clock frequency of the on-chip oscillator depends on the sup-
ply voltage and the operation temperature range.
Be careful that this margin of frequencies when designing applica-
tion products.
6. Ceramic resonator
When the ceramic resonator/quartz-crystal oscillation is used for
the main clock, connect the ceramic resonator and the external
circuit to pins X
resistor is built-in.
7. RC oscillation
When the RC oscillation is used for the main clock, connect the
X
capacitor C at the shortest distance.
The frequency is affected by a capacitor, a resistor and a micro-
computer.
So, set the constants within the range of the frequency limits.
8. External clock
When the external signal clock is used for the main clock, connect
the X
Select “0” (ceramic oscillation) to oscillation mode selection bit.
IN
pin and X
IN
OUT
pin to the clock source and leave X
pin open.
OUT
IN
IN
and X
pin to the external circuit of resistor R and the
pin to V
Rev.1.03
OUT
IN
CC
oscillation control, on-chip oscillator
at the shortest distance. A feedback
through a 1 kΩ to 10 kΩ resistor and
16
Mar 31, 2009
)) is “0” (ceramic/quartz-crys-
OUT
16
) are used to select
pin open.
IN
oscillation
9. Count source (Timer 1, Timer A, Timer X, Serial I/O, A/D con-
verter, Watchdog timer)
The count sources of these functions are affected by the clock di-
vision selection bit of the CPU mode register.
The f(X
f(X
The on-chip oscillator output is supplied to these functions when
selecting the on-chip oscillator output as the CPU clock.
Notes on Oscillation Control
1. Oscillation stop detection circuit
(1) When the stop mode is used, set the oscillation stop detection
(2) When the ceramic or RC oscillation is stopped (bit 4 of CPU
(3) The oscillation stop detection circuit is not included in the emu-
2. Stop mode
(1) When the stop mode is used, set the oscillation stop detection
(2) When the stop mode is used, set “0” to the STP instruction
(3) The oscillation stabilizing time after release of STP instruction
(4) The STP instruction cannot be used when the on-chip oscilla-
(5) When the stop mode is used, set the on-chip oscillator oscilla-
(6) Do not execute the STP instruction during the A/D conversion.
IN
function to “invalid”.
mode register (address 003B
tection function to “invalid”.
lator MCU “M37542RSS”.
function to “invalid”.
function selection bit of the watchdog timer control register (bit
6 of watchdog timer control register (address 0039
can be selected from “set automatically”/“not set automati-
cally” by the oscillation stabilizing time set bit after release of
the STP instruction (bit 0 of MISRG (address 0038
“0” is set to this bit, “01
prescaler 1 automatically at the execution of the STP instruc-
tion. When “1” is set to this bit, set the wait time to timer 1 and
prescaler 1 according to the oscillation stabilizing time of the
oscillation. Also, when timer 1 is used, set values again to
timer 1 and prescaler 1 after system is returned from the stop
mode.
tor is selected by the clock division ratio selection bits (bits 7
and 6 of CPU mode register (address 003B
tion control bit (bit 3 of CPU mode register (address 003B
to “1” (on-chip oscillator oscillation stop).
) as the CPU clock.
IN
) clock is supplied to the watchdog timer when selecting
16
” is set to timer 1 and “FF
16
)), set the oscillation stop de-
16
)).
16
16
16
)).
” is set to
)). When
16
))