M30833FJFP#U3 Renesas Electronics America, M30833FJFP#U3 Datasheet - Page 229

• Manufacturer Part Number: M30833FJFP#U3
• Description: IC M32C/83 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30833FJFP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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16.4 Special Mode 2
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Table 16.19. Special Mode 2 Specifications
0
2
NOTES:
In special mode 2, serial communication between one or multiple masters and multiple slaves is available.
The SSi input pin (i=0 to 4) controls the serial bus communication. Table 16.19 lists specifications of special
mode 2. Table 16.20 lists registers to be used and settings. Tables 16.20 to 16.22 list pin settings.
Transfer Data Format
Transfer Clock
Transmit/Receive Control
Transmit Start Condition
Receive Start Condition
Error Detection
1
Interrupt Request
Generation Timing
Selectable Function
9
C
3 .
B
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
2. To start transmission/reception when selecting the external clock, these conditions must be met after the CKPOL bit
3. If an overrun error occurs, the UiRB register is indeterminate. The IR bit in the SiRIC register does not change to "1"
8 /
0
1
0
3
in the UiC0 register is set to "0" (data is transmitted on the falling edge of the transfer clock and data is received on the
rising edge) and the CLKi pin is held high ("H"), or when the CKPOL bit is set to "1" (Data is transmitted on the rising
edge of the transfer clock and data is received on the falling edge) and the CLKi pin is held low ("L").
(interrupt requested).
_____
3
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4
a
0 -
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3 .
1
u
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3
p
1
2
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0
0
3
6
2
C
Page 204
8 /
, 3
Transfer data : 8 bits long
The CKDIR bit in the UiMR register (i=0 to 4) is set to "0" (internal clock selected) : f
The CKDIR bit to "1" (external clock selected) : input clock from the CLKi pin
______
SSi input pin function
• To start receiving, the following requirement must be met
When data is transferred from the UARTi receive register to the UiRB register (reception completed)
•Overrun error
•Fault error
• LSB first / MSB first
• Continuous receive mode
• Serial data logic inverse
• TxD, RxD I/O polarity Inverse
• Clock phase
• SSi input pin function
•To start transmitting, the following requirements must be met
• Transmit interrupt timing can be selected from the followings:
• Receive interrupt timing
• CLK polarity
f
- Set the RE bit in the UiC1 register to "1" (receive enable)
- Set the TE bit to "1" (receive enable)
- Set the TI bit to "0" (data in the UiTB register)
- Set the TE bit in the UiC1 register to "1" (transmit enable)
- Set the TI bit in the UiC1 register to "0" (data in the UiTB register)
- The UiIRS bit in the UiC1 register is set to "0" (no data in a transmit buffer) :
- The UiIRS register is set to "1" (transmission completed):
This error occurs when the seventh bit of the next received data is read before reading the
In master mode, the fault error occurs an "L" signal is applied to the SSi pin
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Data is transmitted or received in either bit 0 or in bit 7
Reception is enabled simultaneously by reading the UiRB register
This function inverses transmitted or received data logically
TxD pin output and RxD pin input are inversed. All I/O data levels are also inversed
Select from one of 4 combinations of transfer data polarity and phases
Output pin is placed in a high-impedance state to avoid data conflict between master and other
masters or slaves
started)
M
Select from the rising edge or falling edge of the transfer clock when transferred data is output and input
_____
UiRB register
= f
when data is transferred from the UiTB register to the UARTi transmit register (transmission
when data transmission from UARTi transfer register is completed
3
1
2
, f
C
f o
8
8 /
, f
4
2n (1)
8
3
8
) T
(3)
m : setting value of the UiBRG register
Specification
(2)
00
:
(2)
16
16. Serial I/O (Special Function)
:
to FF
______
16
j
/2(m+1)