M30833FJFP#U3 Renesas Electronics America, M30833FJFP#U3 Datasheet - Page 233

• Manufacturer Part Number: M30833FJFP#U3
• Description: IC M32C/83 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30833FJFP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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Figure 16.24 Transmit and Receive Timing in Master Mode (Internal Clock)
0
2
16.4.2 Clock Phase Setting Function
1
9
C
3 .
B
The CKPH bit in the UiSMR3 register (i=0 to 4) and the CKPOL bit in the UiC0 register select one of four
combinations of transfer clock polarity and phases.
The transfer clock phase and polarity must be the same between the master and the slave involved in the
transfer.
8 /
0
1
16.4.2.1 When setting the DINC Bit to "0" (Master (Internal Clock))
16.4.2.2 When Setting the DINC Bit to "1" (Slave (External Clock))
0
3
3
Figure 16.24 shows transmit and receive timing.
When the CKPH bit is set to "0" (no clock delay) and the SSi input pin is held high ("H"), the STxDi pin
is placed in a high-impedance state. When the SSi input pin becomes low ("L"), conditions to start a
serial transfer are met, but output is indeterminate. The serial transmission is synchronized with the
transfer clock. Figure 16.25 shows the transmit and receive timing.
When the CKPH bit is set to "1" (clock delay) and the SSi input pin is held high ("H"), the STxDi pin is
placed in a high-impedance state. When the SSi pin becomes low ("L"), the first data is output. The
serial transmission is synchronized with the transfer clock. Figure 16.26 shows the transmit and
receive timing.
J
G
4
a
0 -
n
o r
3 .
Input Signal to the
SS Pin in the Master
Data Output Timing
Data Input Timing
1
Clock Output
(CKPOL=0, CKPH=0)
Clock Output
(CKPOL=1, CKPH=0)
Clock Output
(CKPOL=0, CKPH=1)
Clock Output
(CKPOL=1, CKPH=1)
u
, 1
3
p
1
2
(
M
0
0
3
6
2
C
Page 208
8 /
, 3
M
3
2
C
"L"
"H"
f o
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"
8 /
4
8
3
8
) T
D
0
D
1
_____
D
_____
2
_____
D
3
_____
D
4
D
5
16. Serial I/O (Special Function)
D
6
D
7