M30833FJFP#U3 Renesas Electronics America, M30833FJFP#U3 Datasheet - Page 385

• Manufacturer Part Number: M30833FJFP#U3
• Description: IC M32C/83 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30833FJFP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
3
. v
J
Figure 23.1 DRAMCONT Register and REFCNT Register
2
0
1
C
9
3 .
B
8 /
0
1
3
0
3
J
G
4
a
0 -
n
o r
DRAM Control Register
DRAM Refresh Interval Set Register
b7
b7
3 .
1
u
Notes:
, 1
3
p
b6
1
1. Contents of the DRAMCONT register is indeterminate. DRAMC starts operation when this register
2. Bus cycle with two waits is 3-2-2.... It is 2-1-1... with one wait.
3. Refer to 23.2.2 Self-refresh for SREF bit setup procedure.
4. The DS register determines the data bus width . CASH is indeterminate when the 8-bit data bus is
2
(
M
0
b5
is written to.
When the SREF bit is set to "1", both RAS and CAS output "L". When any external device,
excluding DRAM, is attached, the WR signal is "L".
selected.
0
3
6
2
b4
C
Page 360
8 /
b3
, 3
b2
M
b1
3
2
C
b0
b0
f o
8 /
4
(b6 - b4)
3
If setting value is n,
Refresh interval = CPU clock cycle X (n + 1) X 32
Symbol
8
SREF
) T
8
AR0
AR1
AR2
WT
Bit
Symbol
DRAMCONT
Symbol
REFCNT
Wait Select Bit
DRAM Area Select Bit
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Self-refresh Mode Bit
Bit Name
Function
Address
0040
Address
0041
(2)
16
16
(3)
b3 b2 b1
0 : 2-wait state
1 : 1-wait state
0 0 0 : Disables DRAM
0 0 1 : Do not set to this value
0 1 0 : 512KB
0 1 1 : 1MB
1 0 0 : 2MB
1 0 1 : 4MB
1 1 0 : 8MB
1 1 1 : Do not set to this value
0 : Self-refresh is off
1 : Self-refresh is on
After Reset
Indeterminate
After Reset
Indeterminate
Function
Setting Range
00
16
(1)
to FF
16
RW
RW
RW
RW
RW
RW
RW
RW
23. DRAMC