M30833FJFP#U3 Renesas Electronics America, M30833FJFP#U3 Datasheet - Page 87

• Manufacturer Part Number: M30833FJFP#U3
• Description: IC M32C/83 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30833FJFP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
3
. v
J
Figure 7.6 ALE Signal and Address/Data Bus
Table 7.6 Microcomputer States in a Wait State
NOTES:
2
0
Oscillation
_____
RD Signal, WR Signal, Address Bus, CSi (i=0 to 3),
Data Bus, ALE Signal, HLDA, Programmable I/O Ports
Internal Peripheral Circuits
7.2.5 ALE Signal
7.2.6 RDY Signal
C
1
9
1. The RDY signal cannot be accepted immediately before software wait states are inserted.
3 .
B
8 /
The ALE signal latches an address of the multiplexed bus. Latch an address on the falling edge of the
ALE signal. The PM15 to PM14 bits in the PM1 register determine the output pin for the ALE signal.
The ALE signal is output to an internal space and external space.
The RDY signal facilitates access to external devices which need longer access time. When an "L" signal
is applied to the RDY pin on the falling edge of last BCLK of the bus cycle, wait states are inserted into the
bus cycle. When an "H" signal is applied to the RDY pin on the falling edge of the BCLK, the bus cycle
starts running again.
Table 7.6 lists microcomputer states when the RDY signal inserts wait states into the bus cycle. Figure
7.7 shows an example of the RD signal extended by the RDY signal.
D
0
1
3
0
0
(1) 8-Bit Data Bus
/A
3
J
G
A
4
a
0
_______
A
o r
0 -
16
n
A
A
A
A
_______
to D
8
________
3 .
20
21
22
23
1
u
to A
to A
, 1
3
p
/CS3
/CS2
/CS1
/CS0
_____
ALE
7
1
/A
(
2
15
M
19
0
7
0
3
6
NOTES:
2
________
C
1. D
2. When the multiplexed bus is selected for all CS areas, the address bus becomes an I/O port.
8 /
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, 3
Address
0
__________
/A
M
0
3
to D
Item
Address or CS
2
C
f o
Address
Address
7
8 /
/A
4
_____
3
7
8
) T
8
are placed in high-impedance state when read.
(2)
_____
Data
(1)
________
________
(1)
D
0
/A
0
________
On
Maintains the same state as when RDY signal
was received
On
to D
A
(2) 16-Bit Data Bus
16
A
A
A
A
20
21
22
23
15
to A
/CS3
/CS2
/CS1
/CS0
ALE
/A
19
15
Address
Address or CS
State
Address
(2)
Data
________
(1)
7. Bus