ATMEGA8L-8PU Atmel, ATMEGA8L-8PU Datasheet

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... PDIP, 32-lead TQFP, and 32-pad MLF • Operating Voltages – 2.7 - 5.5V (ATmega8L) – 4.5 - 5.5V (ATmega8) • Speed Grades – MHz (ATmega8L) – MHz (ATmega8) • Power Consumption at 4 Mhz, 3V, 25°C – Active: 3.6 mA – Idle Mode: 1.0 mA – Power-down Mode: 0.5 µA ® ...

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Pin Configurations ATmega8(L) 2 PDIP (RESET) PC6 1 28 PC5 (ADC5/SCL) (RXD) PD0 2 27 PC4 (ADC4/SDA) (TXD) PD1 3 26 PC3 (ADC3) (INT0) PD2 4 25 PC2 (ADC2) (INT1) PD3 5 24 PC1 (ADC1) (XCK/T0) PD4 6 23 PC0 ...

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Overview Block Diagram 2486O–AVR–10/04 The ATmega8 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega8 achieves throughputs approaching 1 MIPS per MHz, allowing the system designer ...

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... Section will continue to run while the Application Flash Section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self- Programmable Flash on a monolithic chip, the Atmel ATmega8 is a powerful microcon- troller that provides a highly-flexible and cost-effective solution to many embedded control applications ...

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Pin Descriptions VCC GND Port B (PB7..PB0) XTAL1/XTAL2/TOSC1/TOSC2 Port C (PC5..PC0) PC6/RESET Port D (PD7..PD0) RESET 2486O–AVR–10/04 Digital supply voltage. Ground. Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B ...

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AV CC AREF ADC7..6 (TQFP and MLF Package Only) About Code Examples ATmega8( the supply voltage pin for the A/D Converter, Port C (3..0), and ADC (7..6 should be externally connected should ...

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AVR CPU Core Introduction Architectural Overview 2486O–AVR–10/04 This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, ...

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ATmega8(L) 8 Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer ...

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Arithmetic Logic Unit – ALU Status Register 2486O–AVR–10/04 The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and ...

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General Purpose Register File ATmega8(L) 10 The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates ...

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The X-register, Y-register and Z-register Stack Pointer 2486O–AVR–10/04 The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y ...

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Instruction Execution Timing Reset and Interrupt Handling ATmega8(L) 12 This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk source for the chip. No internal clock division is used. ...

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Flash section by setting the Interrupt Vector Select (IVSEL) bit in the General Interrupt Control Register (GICR). Refer to “Interrupts” on page 44 for more information. The Reset Vector can also be moved to the start ...

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Interrupt Response Time ATmega8(L) 14 When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in the following example. Assembly Code Example sei ; set global interrupt enable sleep; ...

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AVR ATmega8 Memories In-System Reprogrammable Flash Program Memory 2486O–AVR–10/04 This section describes the different memories in the ATmega8. The AVR architecture has two main memory spaces, the Data memory and the Program Memory space. In addition, the ATmega8 features an ...

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SRAM Data Memory ATmega8(L) 16 Figure 8 shows how the ATmega8 SRAM Memory is organized. The lower 1120 Data memory locations address the Register File, the I/O Memory, and the internal data SRAM. The first 96 locations address the Register ...

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Data Memory Access Times EEPROM Data Memory EEPROM Read/Write Access 2486O–AVR–10/04 This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk 9. Figure 9. On-chip Data SRAM Access ...

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The EEPROM Address Register – EEARH and EEARL The EEPROM Data Register – EEDR The EEPROM Control Register – EECR ATmega8(L) 18 Bit – – – EEAR7 EEAR6 EEAR5 Read/Write R/W ...

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EEPROM. The EEMWE bit must be written to one before a logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of ...

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ATmega8(L) 20 The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (for example by dis- abling interrupts globally) so that no interrupts will occur during execution ...

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EEPROM Write during Power- down Sleep Mode Preventing EEPROM Corruption 2486O–AVR–10/04 The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of ...

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I/O Memory ATmega8(L) 22 Keep the AVR RESET active (low) during periods of insufficient power supply volt- age. This can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match ...

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System Clock and Clock Options Clock Systems and their Distribution CPU Clock – clk CPU I/O Clock – clk I/O Flash Clock – clk FLASH 2486O–AVR–10/04 Figure 10 presents the principal clock systems in the AVR and their distribution. All ...

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Asynchronous Timer Clock – clk ASY ADC Clock – clk ADC Clock Sources ATmega8(L) 24 The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external 32 kHz clock crystal. The dedicated clock domain allows using ...

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Crystal Oscillator 2486O–AVR–10/04 XTAL1 and XTAL2 are input and output, respectively inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 11. Either a quartz crystal or a ceramic resonator may be ...

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Low-frequency Crystal Oscillator ATmega8(L) 26 Table 5. Start-up Times for the Crystal Oscillator Clock Selection Start-up Time from Power-down CKSEL0 SUT1..0 and Power-save ( 258 CK ( 258 CK ( (2) 0 ...

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External RC Oscillator 2486O–AVR–10/04 For timing insensitive applications, the external RC configuration shown in Figure 12 can be used. The frequency is roughly estimated by the equation f = 1/(3RC). C should be at least 22 pF. By programming the ...

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... Oscillator. At 5V, 25°C and 1.0 MHz Oscillator frequency selected, this calibration gives a frequency within ± the nominal frequency. Using run-time calibration methods as described in application notes available at www.atmel.com/avr it is possible to achieve ± 1% accuracy at any given V as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed calibration value, see the section “ ...

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Oscillator Calibration Register – OSCCAL 2486O–AVR–10/04 Bit CAL7 CAL6 CAL5 Read/Write R/W R/W R/W Initial Value • Bits 7..0 – CAL7..0: Oscillator Calibration Value Writing the calibration byte to this address will trim the Internal Oscillator to ...

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External Clock Timer/Counter Oscillator ATmega8( drive the device from an external clock source, XTAL1 should be driven as shown in Figure 13. To run the device on an external clock, the CKSEL Fuses must be pro- grammed to ...

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Power Management and Sleep Modes MCU Control Register – MCUCR 2486O–AVR–10/04 Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power ...

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Idle Mode ADC Noise Reduction Mode Power-down Mode Power-save Mode ATmega8(L) 32 When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing SPI, USART, Analog Comparator, ADC, Two- ...

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Standby Mode Table 14. Active Clock Domains and Wake-up Sources in the Different Sleep Modes Active Clock Domains Sleep clk clk clk Mode CPU FLASH IO Idle X ADC Noise Reduction Power Down Power Save (1) Standby Notes: 1. External ...

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Brown-out Detector Internal Voltage Reference Watchdog Timer Port Pins ATmega8( the Brown-out Detector is not needed in the application, this module should be turned off. If the Brown-out Detector is enabled by the BODEN Fuse, it will be ...

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System Control and Reset Resetting the AVR Reset Sources 2486O–AVR–10/04 During Reset, all I/O Registers are set to their initial values, and the program starts exe- cution from the Reset Vector. If the program never enables an interrupt source, the ...

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... V production test. This guarantees that a Brown-out Reset will occur before voltage where correct operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL = 1 for ATmega8L and BODLEVEL = 0 for ATmega8. BODLEVEL = 1 is not applicable for ATmega8. DATA BUS ...

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Power-on Reset 2486O–AVR–10/04 A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detec- tion level is defined in Table 15. The POR is activated whenever V detection level. The POR circuit can be used to trigger ...

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External Reset Brown-out Detection ATmega8( External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Table 15) will generate a reset, even if the clock is not ...

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Watchdog Reset MCU Control and Status Register – MCUCSR 2486O–AVR–10/04 When the Watchdog times out, it will generate a short reset pulse cycle dura- tion. On the falling edge of this pulse, the delay timer starts counting ...

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Internal Voltage Reference Voltage Reference Enable Signals and Start-up Time ATmega8(L) 40 ATmega8 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. ...

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Watchdog Timer Watchdog Timer Control Register – WDTCR 2486O–AVR–10/04 The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 MHz. This is the typical value other V levels. By controlling the Watchdog Timer ...

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ATmega8(L) 42 • Bit 3 – WDE: Watchdog Enable When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written to logic zero, the Watchdog Timer function is disabled. WDE can only ...

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Timed Sequences for Changing the Configuration of the Watchdog Timer Safety Level 1 (WDTON Fuse Unprogrammed) Safety Level 2 (WDTON Fuse Programmed) 2486O–AVR–10/04 The sequence for changing the Watchdog Timer configuration differs slightly between the safety levels. Separate procedures are ...

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Interrupts Interrupt Vectors in ATmega8 ATmega8(L) 44 This section describes the specifics of the interrupt handling performed by the ATmega8. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 12. Table 18. ...

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Table 19. Reset and Interrupt Vectors Placement (1) BOOTRST IVSEL Reset Address 1 0 0x000 1 1 0x000 0 0 Boot Reset Address 0 1 Boot Reset Address Note: 1. The Boot Reset Address is shown in Table 82 ...

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ATmega8(L) 46 When the BOOTRST Fuse is unprogrammed, the boot section size set to 2K bytes and the IVSEL bit in the GICR Register is set before any interrupts are enabled, the most typical and general program setup for the ...

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Moving Interrupts Between Application and Boot Space General Interrupt Control Register – GICR 2486O–AVR–10/04 When the BOOTRST Fuse is programmed, the boot section size set to 2K bytes, and the IVSEL bit in the GICR Register is set before any ...

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ATmega8(L) 48 • Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when ...

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I/O Ports Introduction 2486O–AVR–10/04 All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without uninten- tionally changing the direction of any other pin ...

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Ports as General Digital I/O Configuring the Pin ATmega8(L) 50 The ports are bi-directional I/O ports with optional internal pull-ups. Figure 22 shows a functional description of one I/O port pin, here generically called Pxn. (1) Figure 22. General Digital ...

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Reading the Pin Value 2486O–AVR–10/04 When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled ({DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. ...

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ATmega8(L) 52 Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region ...

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Digital Input Enable and Sleep Modes 2486O–AVR–10/04 The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from input with pull-ups assigned ...

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Unconnected pins Alternate Port Functions ATmega8( some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described ...

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Table 21 summarizes the function of the overriding signals. The pin and port indexes from Figure 25 are not shown in the succeeding tables. The overriding signals are gen- erated internally in the modules having the alternate function. Table ...

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Special Function IO Register – SFIOR Alternate Functions of Port B ATmega8(L) 56 Bit Read/Write Initial Value • Bit 2 – PUD: Pull-up Disable When this bit is written to one, ...

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Oscillator amplifier. In this mode, a crystal Oscillator is connected to this pin, and the pin can not be used as an I/O pin. If PB6 is used as a clock pin, DDB6, PORTB6 and PINB6 will all ...

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ATmega8(L) 58 Table 23. Overriding Signals for Alternate Functions in PB7..PB4 Signal PB7/XTAL2/ PB6/XTAL1/ (1)(2) Name TOSC2 TOSC1 PUOE EXT • (INTRC + INTRC + AS2 AS2) PUO 0 0 DDOE EXT • (INTRC + INTRC + AS2 AS2) DDOV ...

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Alternate Functions of Port C 2486O–AVR–10/04 The Port C pins with alternate functions are shown in Table 25. Table 25. Port C Pins Alternate Functions Port Pin Alternate Function PC6 RESET (Reset pin) ADC5 (ADC Input Channel 5) PC5 SCL ...

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ATmega8(L) 60 PC1 can also be used as ADC input Channel 1. Note that ADC input channel 1 uses analog power. • ADC0 – Port C, Bit 0 PC0 can also be used as ADC input Channel 0. Note that ...

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Alternate Functions of Port D 2486O–AVR–10/04 The Port D pins with alternate functions are shown in Table 28. Table 28. Port D Pins Alternate Functions Port Pin Alternate Function PD7 AIN1 (Analog Comparator Negative Input) PD6 AIN0 (Analog Comparator Positive ...

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ATmega8(L) 62 Table 29 and Table 30 relate the alternate functions of Port D to the overriding signals shown in Figure 25 on page 54. Table 29. Overriding Signals for Alternate Functions PD7..PD4 Signal Name PD7/AIN1 PD6/AIN0 PUOE 0 0 ...

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Register Description for I/O Ports The Port B Data Register – PORTB The Port B Data Direction Register – DDRB The Port B Input Pins Address – PINB The Port C Data Register – PORTC The Port C Data Direction ...

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External Interrupts MCU Control Register – MCUCR ATmega8(L) 64 The external interrupts are triggered by the INT0, and INT1 pins. Observe that, if enabled, the interrupts will trigger even if the INT0..1 pins are configured as outputs. This feature provides ...

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General Interrupt Control Register – GICR 2486O–AVR–10/04 • Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the ...

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General Interrupt Flag Register – GIFR ATmega8(L) 66 Bit INTF1 INTF0 – Read/Write R/W R/W R Initial Value • Bit 7 – INTF1: External Interrupt Flag 1 When an event on the INT1 pin ...

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Timer/Counter0 Overview Registers Definitions 2486O–AVR–10/04 Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: • Single Channel Counter • Frequency Generator • External Event Counter • 10-bit Clock Prescaler A simplified block diagram of ...

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Timer/Counter Clock Sources Counter Unit Operation ATmega8(L) 68 The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the clock select logic which is controlled by the clock select (CS02:0) bits ...

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Timer/Counter Timing Diagrams 2486O–AVR–10/04 The Timer/Counter is a synchronous design and the timer clock (clk shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set. Figure 28 contains timing data ...

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Timer/Counter Register Description Timer/Counter Control Register – TCCR0 Timer/Counter Register – TCNT0 Timer/Counter Interrupt Mask Register – TIMSK ATmega8(L) 70 Bit – – – Read/Write Initial Value • Bit 2:0 ...

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Timer/Counter Interrupt Flag Register – TIFR 2486O–AVR–10/04 Bit OCF2 TOV2 ICF1 Read/Write R/W R/W R/W Initial Value • Bit 0 – TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set (one) when an overflow ...

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Timer/Counter0 and Timer/Counter1 Prescalers Internal Clock Source Prescaler Reset External Clock Source ATmega8(L) 72 Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. The ...

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Special Function IO Register – SFIOR 2486O–AVR–10/04 Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system ...

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Timer/Counter1 Overview ATmega8(L) 74 The 16-bit Timer/Counter unit allows accurate program execution timing (event man- agement), wave generation, and signal timing measurement. The main features are: • True 16-bit Design (i.e., allows 16-bit PWM) • Two Independent Output Compare ...

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Registers 2486O–AVR–10/04 Figure 32. 16-bit Timer/Counter Block Diagram Count Clear Direction Timer/Counter TCNTn = OCRnA = OCRnB ICRn TCCRnA Note: 1. Refer to “Pin Configurations” on page 2, Table 22 on page 56, and Table 28 on page 61 for ...

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Definitions Compatibility ATmega8(L) 76 set the Compare Match Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the ...

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Accessing 16-bit Registers 2486O–AVR–10/04 The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. The 16-bit ...

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ATmega8(L) 78 The following code examples show how atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle. (1) Assembly Code Example TIM16_ReadTCNT1: ; ...

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Reusing the Temporary High Byte Register 2486O–AVR–10/04 The following code examples show how atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. (1) ...

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Timer/Counter Clock Sources Counter Unit ATmega8(L) 80 The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the clock select logic which is controlled by the clock select (CS12:0) bits located ...

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Input Capture Unit 2486O–AVR–10/04 The counting sequence is determined by the setting of the Waveform Generation mode bits (WGM13:0) located in the Timer/Counter Control Registers A and B (TCCR1A and TCCR1B). There are close connections between how the counter behaves ...

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Input Capture Pin Source Noise Canceler Using the Input Capture Unit ATmega8(L) 82 Reading the 16-bit value in the Input Capture Register (ICR1) is done by first reading the Low byte (ICR1L) and then the High byte (ICR1H). When the ...

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Output Compare Units 2486O–AVR–10/04 (ICF1) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICF1 Flag is not required (if an interrupt handler is used). The 16-bit ...

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Force Output Compare Compare Match Blocking by TCNT1 Write Using the Output Compare Unit ATmega8(L) 84 update of the OCR1x Compare Register to either TOP or BOTTOM of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM ...

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Compare Match Output Unit 2486O–AVR–10/04 The Compare Output mode (COM1x1:0) bits have two functions. The waveform genera- tor uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next Compare Match. Secondly the COM1x1:0 bits control the ...

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Compare Output Mode and Waveform Generation Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode ATmega8(L) 86 The waveform generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM1x1:0 ...

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Fast PWM Mode 2486O–AVR–10/04 Figure 37. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period 1 An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 Flag according to ...

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ATmega8(L) 88 quency allows physically small sized external components (coils, capacitors), hence reduces total system cost. The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution ...

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Phase Correct PWM Mode 2486O–AVR–10/04 ing at 0x0000 before the Compare Match can occur. The OCR1A Register, however, is double buffered. This feature allows the OCR1A I/O location to be written anytime. When the OCR1A I/O location is written the ...

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ATmega8(L) 90 OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation: R PCPWM In phase correct PWM mode the counter ...

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Phase and Frequency Correct PWM Mode 2486O–AVR–10/04 period will differ in length. The difference in length gives the unsymmetrical result on the output recommended to use the Phase and Frequency Correct mode instead of the Phase Correct mode ...

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ATmega8(L) 92 (WGM13:0 = 9). The counter has then reached the TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency correct ...

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Timer/Counter Timing Diagrams 2486O–AVR–10/ See Table 38 on page 96. The actual OC1x value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform ...

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ATmega8(L) 94 Figure 42. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn OCRnx - 1 OCRnx OCFnx Figure 43 shows the count sequence close to TOP in various modes. When using ...

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Timer/Counter Register Description Timer/Counter 1 Control Register A – TCCR1A 2486O–AVR–10/04 Figure 44. Timer/Counter Timing Diagram, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn TOP - 1 (CTC and FPWM) TCNTn TOP - 1 (PC and ...

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ATmega8(L) 96 Table 37 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast PWM mode. Table 37. Compare Output Mode, Fast PWM COM1A1/ COM1A0/ COM1B1 COM1B0 Description 0 0 Normal port operation, OC1A/OC1B disconnected. 0 ...

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Table 39. Waveform Generation Mode Bit Description WGM12 WGM11 Mode WGM13 (CTC1) (PWM11 ...

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Timer/Counter 1 Control Register B – TCCR1B ATmega8(L) 98 Bit ICNC1 ICES1 – Read/Write R/W R/W R Initial Value • Bit 7 – ICNC1: Input Capture Noise Canceler Setting this bit (to one) activates ...

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Timer/Counter 1 – TCNT1H and TCNT1L Output Compare Register 1 A – OCR1AH and OCR1AL Output Compare Register 1 B – OCR1BH and OCR1BL 2486O–AVR–10/04 If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will ...

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Input Capture Register 1 – ICR1H and ICR1L Timer/Counter Interrupt Mask (1) Register – TIMSK ATmega8(L) 100 Bit Read/Write R/W R/W R/W Initial Value The Input Capture is updated with the counter (TCNT1) value ...

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Timer/Counter Interrupt Flag (1) Register – TIFR 2486O–AVR–10/04 Bit OCF2 TOV2 ICF1 Read/Write R/W R/W R/W Initial Value Note: 1. This register contains flag bits for several Timer/Counters, but only Timer1 bits are described ...

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Timer/Counter2 with PWM and Asynchronous Operation Overview ATmega8(L) 102 Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, phase Correct ...

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Registers Definitions Timer/Counter Clock Sources 2486O–AVR–10/04 The Timer/Counter (TCNT2) and Output Compare Register (OCR2) are 8-bit registers. Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the ...

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Counter Unit ATmega8(L) 104 The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 46 shows a block diagram of the counter and its surrounding environment. Figure 46. Counter Unit Block Diagram DATA BUS count clear ...

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Output Compare Unit 2486O–AVR–10/04 The 8-bit comparator continuously compares TCNT2 with the Output Compare Register (OCR2). Whenever TCNT2 equals OCR2, the comparator signals a match. A match will set the Output Compare Flag (OCF2) at the next timer clock cycle. ...

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Force Output Compare Compare Match Blocking by TCNT2 Write Using the Output Compare Unit ATmega8(L) 106 In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC2) ...

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Compare Match Output Unit 2486O–AVR–10/04 The Compare Output mode (COM21:0) bits have two functions. The waveform genera- tor uses the COM21:0 bits for defining the Output Compare (OC2) state at the next Compare Match. Also, the COM21:0 bits control the ...

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Compare Output Mode and Waveform Generation Modes of Operation Normal Mode ATmega8(L) 108 The Waveform Generator uses the COM21:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM21 tells the waveform generator that ...

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Clear Timer on Compare Match (CTC) Mode 2486O–AVR–10/04 In Clear Timer on Compare or CTC mode (WGM21:0 = 2), the OCR2 Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the ...

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Fast PWM Mode ATmega8(L) 110 The fast Pulse Width Modulation or fast PWM mode (WGM21 provides a high fre- quency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The ...

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Phase Correct PWM Mode 2486O–AVR–10/04 The PWM frequency for the output can be calculated by the following equation: The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR2 Register ...

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ATmega8(L) 112 Figure 51. Phase Correct PWM Mode, Timing Diagram TCNTn OCn OCn Period 1 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOT- TOM. The Interrupt Flag can be used to generate an interrupt each ...

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Timer/Counter Timing Diagrams 2486O–AVR–10/04 • The timer starts counting from a value higher than the one in OCR2A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. The ...

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ATmega8(L) 114 Figure 54. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn OCRn - 1 OCRn OCFn Figure 55 shows the setting of OCF2 and the clearing of TCNT2 in CTC ...

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Timer/Counter Register Description Timer/Counter Control Register – TCCR2 2486O–AVR–10/04 Bit FOC2 WGM20 COM21 Read/Write W R/W R/W Initial Value • Bit 7 – FOC2: Force Output Compare The FOC2 bit is only active ...

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ATmega8(L) 116 Table 43. Compare Output Mode, Non-PWM Mode COM21 COM20 Description 0 0 Normal port operation, OC2 disconnected Toggle OC2 on Compare Match 1 0 Clear OC2 on Compare Match 1 1 Set OC2 on Compare Match ...

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Timer/Counter Register – TCNT2 Output Compare Register – OCR2 Asynchronous Operation of the Timer/Counter Asynchronous Status Register – ASSR 2486O–AVR–10/04 • Bit 2:0 – CS22:0: Clock Select The three clock select bits select the clock source to be used by ...

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Asynchronous Operation of Timer/Counter2 ATmega8(L) 118 • Bit 2 – TCN2UB: Timer/Counter2 Update Busy When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set. When TCNT2 has been updated from the temporary storage register, this bit is cleared ...

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This is particularly important if the Output Compare2 interrupt is used to wake up the device, since the Output Compare function is disabled during writing to OCR2 or TCNT2. If the write cycle is not finished, ...

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Timer/Counter Interrupt Mask Register – TIMSK Timer/Counter Interrupt Flag Register – TIFR ATmega8(L) 120 Bit OCIE2 TOIE2 TICIE1 Read/Write R/W R/W R/W Initial Value • Bit 7 – OCIE2: Timer/Counter2 Output Compare Match Interrupt ...

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Timer/Counter Prescaler Special Function IO Register – SFIOR 2486O–AVR–10/04 Figure 56. Prescaler for Timer/Counter2 clk clk I/O T2S TOSC1 AS2 PSR2 CS20 CS21 CS22 The clock source for Timer/Counter2 is named clk the main system I/O clock clk . By ...

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Serial Peripheral Interface – SPI ATmega8(L) 122 The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega8 and peripheral devices or between several AVR devices. The ATmega8 SPI includes the following features: • Full-duplex, Three-wire Synchronous Data ...

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When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by user software before communication can start. When this is done, writing a byte to the SPI Data Register ...

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ATmega8(L) 124 The following code examples show how to initialize the SPI as a Master and how to per- form a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. ...

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The following code examples show how to initialize the SPI as a Slave and how to per- form a simple reception. (1) Assembly Code Example SPI_SlaveInit: ; Set MISO output, all others input ldi r17,(1<<DD_MISO) out DDR_SPI,r17 ; Enable ...

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SS Pin Functionality Slave Mode Master Mode SPI Control Register – SPCR ATmega8(L) 126 When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and ...

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SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Master mode. • Bit 3 – CPOL: Clock Polarity When this bit is written to one, SCK is high ...

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SPI Status Register – SPSR SPI Data Register – SPDR ATmega8(L) 128 Bit SPIF WCOL – Read/Write Initial Value • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer ...

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Data Modes 2486O–AVR–10/04 There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 59 and Figure 60. Data ...

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USART Overview ATmega8(L) 130 The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART highly-flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • ...

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AVR USART vs. AVR UART – Compatibility Clock Generation 2486O–AVR–10/04 The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock generator, Transmitter and Receiver. Control Registers are shared by all ...

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Internal Clock Generation – The Baud Rate Generator ATmega8(L) 132 Figure 62. Clock Generation Logic, Block Diagram UBRR UBRR+1 Prescaling Down-Counter OSC Sync Register xcki XCK xcko Pin DDR_XCK Signal description: txclk Transmitter clock. (Internal Signal) rxclk Receiver base clock. ...

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Double Speed Operation (U2X) External Clock 2486O–AVR–10/04 Table 52. Equations for Calculating Baud Rate Register Setting Equation for Calculating Operating Mode Asynchronous Normal mode BAUD (U2X = 0) Asynchronous Double Speed Mode (U2X = 1) BAUD Synchronous Master Mode BAUD ...

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Synchronous Clock Operation When Synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock Frame Formats ATmega8(L) 134 input (Slave) or clock output (Master). The dependency between the clock edges and data sampling or ...

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Parity Bit Calculation USART Initialization 2486O–AVR–10/04 Sp Stop bit, always high. IDLE No transfers on the communication line (RxD or TxD). An IDLE line must be high. The frame format used by the USART is set by the UCSZ2:0, UPM1:0 ...

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ATmega8(L) 136 (1) Assembly Code Example USART_Init: ; Set baud rate out UBRRH, r17 out UBRRL, r16 ; Enable Receiver and Transmitter ldi r16, (1<<RXEN)|(1<<TXEN) out UCSRB,r16 ; Set frame format: 8data, 2stop bit ldi r16, (1<<URSEL)|(1<<USBS)|(3<<UCSZ0) out UCSRC,r16 ret ...

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Data Transmission – The USART Transmitter Sending Frames with Data Bits 2486O–AVR–10/04 The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRB Register. When the Transmitter is enabled, the normal port operation ...

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Sending Frames with 9 Data Bits Transmitter Flags and Interrupts ATmega8(L) 138 If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in UCSRB before the Low byte of the character is ...

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Parity Generator Disabling the Transmitter 2486O–AVR–10/04 interrupt-driven data transmission is used, the Data Register empty Interrupt routine must either write new data to UDR in order to clear UDRE or disable the Data Register empty Interrupt, otherwise a new interrupt ...

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Data Reception – The USART Receiver Receiving Frames with Data Bits ATmega8(L) 140 The USART Receiver is enabled by writing the Receive Enable (RXEN) bit in the UCSRB Register to one. When the Receiver is enabled, the ...

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Receiving Frames with 9 Data Bits 2486O–AVR–10/04 If 9-bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8 bit in UCSRB before reading the low bits from the UDR. This rule applies to the FE, DOR ...

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ATmega8(L) 142 The following code example shows a simple USART receive function that handles both 9-bit characters and the status bits. (1) Assembly Code Example USART_Receive: ; Wait for data to be received sbis UCSRA, RXC rjmp USART_Receive ; Get ...

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Receive Compete Flag and Interrupt Receiver Error Flags 2486O–AVR–10/04 The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXC) Flag indicates if there are unread data present in the receive buffer. This flag is one ...

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Parity Checker Disabling the Receiver Flushing the Receive Buffer Asynchronous Data Reception Asynchronous Clock Recovery ATmega8(L) 144 The Parity Checker is active when the high USART Parity mode (UPM1) bit is set. Type of parity check to be performed (odd ...

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Asynchronous Data Recovery 2486O–AVR–10/04 (U2X = 1) of operation. Samples denoted zero are samples done when the RxD line is idle (i.e., no communication activity). Figure 65. Start Bit Sampling RxD IDLE Sample (U2X = ...

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Asynchronous Operational Range ATmega8(L) 146 Figure 67. Stop Bit Sampling and Next Start Bit Sampling RxD Sample (U2X = Sample (U2X = The same majority voting is done to the ...

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Table 53. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2X = 0) D# (Data+Parity Bit) R (%) R slow 5 93,20 106,67 6 94,12 105,79 7 94,81 105,11 8 95,36 104,58 9 95,81 104,14 10 96,17 ...

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Multi-processor Communication Mode Using MPCM ATmega8(L) 148 Setting the Multi-processor Communication mode (MPCM) bit in UCSRA enables a fil- tering function of incoming frames received by the USART Receiver. Frames that do not contain address information will be ignored and ...

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Accessing UBRRH/UCSRC Registers Write Access 2486O–AVR–10/04 The UBRRH Register shares the same I/O location as the UCSRC Register. Therefore some special consideration must be taken when accessing this I/O location. When doing a write access of this I/O location, the ...

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Read Access USART Register Description USART I/O Data Register – UDR ATmega8(L) 150 Doing a read access to the UBRRH or the UCSRC Register is a more complex opera- tion. However, in most applications rarely necessary to read ...

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USART Control and Status Register A – UCSRA 2486O–AVR–10/04 The transmit buffer can only be written when the UDRE Flag in the UCSRA Register is set. Data written to UDR when the UDRE Flag is not set, will be ignored ...

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USART Control and Status Register B – UCSRB ATmega8(L) 152 This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud ...

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USART Control and Status Register C – UCSRC 2486O–AVR–10/04 TXB8 is the ninth data bit in the character to be transmitted when operating with serial frames with nine data bits. Must be written before writing the low bits to UDR. ...

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ATmega8(L) 154 • Bit 5:4 – UPM1:0: Parity Mode These bits enable and set type of Parity Generation and Check. If enabled, the Trans- mitter will automatically generate and send the parity of the transmitted data bits within each frame. ...

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USART Baud Rate Registers – UBRRL and UBRRHs 2486O–AVR–10/04 This bit is used for Synchronous mode only. Write this bit to zero when Asynchronous mode is used. The UCPOL bit sets the relationship between data output change and data input ...

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Examples of Baud Rate Setting Table 60. Examples of UBRR Settings for Commonly Used Oscillator Frequencies f = 1.0000 MHz osc Baud U2X = 0 U2X = 1 Rate (bps) UBRR Error UBRR 2400 25 0.2% 51 4800 12 0.2% ...

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Table 61. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 3.6864 MHz osc Baud U2X = 0 Rate (bps) UBRR Error UBRR 2400 95 0.0% 191 4800 47 0.0% 95 9600 23 0.0% 47 14.4k 15 ...

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Table 62. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 8.0000 MHz osc Baud U2X = 0 U2X = 1 Rate (bps) UBRR Error UBRR 2400 207 0.2% 416 4800 103 0.2% 207 9600 51 0.2% ...

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Table 63. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 16.0000 MHz osc Baud U2X = 0 Rate (bps) UBRR Error UBRR 2400 416 -0.1% 832 4800 207 0.2% 416 9600 103 0.2% 207 14.4k 68 ...

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Two-wire Serial Interface Features Two-wire Serial Interface Bus Definition TWI Terminology ATmega8(L) 160 • Simple Yet Powerful and Flexible Communication Interface, only two Bus Lines Needed • Both Master and Slave Operation Supported • Device can Operate as Transmitter or ...

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Electrical Interconnection Data Transfer and Frame Format Transferring Bits START and STOP Conditions 2486O–AVR–10/04 As depicted in Figure 68, both bus lines are connected to the positive supply voltage through pull-up resistors. The bus drivers of all TWI-compliant devices are ...

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Address Packet Format ATmega8(L) 162 Figure 70. START, REPEATED START and STOP conditions SDA SCL START All address packets transmitted on the TWI bus are 9 bits long, consisting of 7 address bits, one READ/WRITE control bit and an acknowledge ...

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Data Packet Format Combining Address and Data Packets into a Transmission Figure 73. Typical Data Transmission Addr MSB SDA SCL 1 2 START SLA+R/W 2486O–AVR–10/04 All data packets transmitted on the TWI bus are nine bits long, consisting of one ...

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Multi-master Bus Systems, Arbitration and Synchronization ATmega8(L) 164 The TWI protocol allows bus systems with several masters. Special concerns have been taken in order to ensure that transmissions will proceed as normal, even if two or more masters initiate a ...

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Figure 75. Arbitration Between Two Masters START SDA from Master A SDA from Master B SDA Line Synchronized SCL Line Note that arbitration is not allowed between: • A REPEATED START condition and a data bit. • A STOP ...

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Overview of the TWI Module SCL and SDA Pins ATmega8(L) 166 The TWI module is comprised of several submodules, as shown in Figure 76. All regis- ters drawn in a thick line are accessible through the AVR data bus. Figure ...

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Bit Rate Generator Unit Bus Interface Unit Address Match Unit Control Unit 2486O–AVR–10/04 This unit controls the period of SCL when operating in a Master mode. The SCL period is controlled by settings in the TWI Bit Rate Register (TWBR) ...

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TWI Register Description TWI Bit Rate Register – TWBR TWI Control Register – TWCR ATmega8(L) 168 Interrupt Flag is asserted. At all other times, the TWSR contains a special status code indicating that no relevant status information is available. As ...

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The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is writ- ten to one, the ACK pulse is generated on the TWI bus if the following conditions are met: 1. The device’s own slave ...

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TWI Status Register – TWSR TWI Data Register – TWDR TWI (Slave) Address Register – TWAR ATmega8(L) 170 Bit TWS7 TWS6 TWS5 Read/Write Initial Value • Bits 7..3 – TWS: TWI ...

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Using the TWI 2486O–AVR–10/04 TWA6 TWA5 TWA4 Read/Write R/W R/W R/W Initial Value The TWAR should be loaded with the 7-bit Slave address (in the seven most significant bits of TWAR) to which the TWI will respond ...

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Figure 77. Interfacing the Application to the TWI in a Typical Transmission 3. Check TWSR to see if START was 1. Application sent. Application loads SLA+W into writes to TWCR to TWDR, and loads appropriate control initiate signals into TWCR, ...

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However important that the TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will not start any opera- tion as long as the TWINT bit ...

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Assembly Code Example ldi r16, (1<<TWINT)|(1<<TWSTA)| 1 (1<<TWEN) out TWCR, r16 wait1 r16,TWCR sbrs r16,TWINT rjmp wait1 in r16,TWSR 3 andi r16, 0xF8 cpi r16, START brne ERROR ldi r16, SLA_W out TWDR, r16 ldi r16, (1<<TWINT) | ...

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Transmission Modes 2486O–AVR–10/04 The TWI can operate in one of four major modes. These are named Master Transmitter (MT), Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of these modes can be used in the same application. ...

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Master Transmitter Mode ATmega8(L) 176 In the Master Transmitter mode, a number of data bytes are transmitted to a Slave Receiver (see Figure 78). In order to enter a Master mode, a START condition must be transmitted. The format of ...

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Table 66. Status codes for Master Transmitter Mode Status Code (TWSR) Status of the Two-wire Serial Prescaler Bits Bus and Two-wire Serial Inter- are 0 face Hardware 0x08 A START condition has been transmitted 0x10 A repeated START condition has ...

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ATmega8(L) 178 Figure 79. Formats and States in the Master Transmitter Mode MT Successfull S SLA W transmission to a slave receiver $08 Next transfer started with a repeated start condition Not acknowledge received after the slave address Not acknowledge ...

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Master Receiver Mode 2486O–AVR–10/04 In the Master Receiver mode, a number of data bytes are received from a Slave Trans- mitter (see Figure 80). In order to enter a Master mode, a START condition must be transmitted. The format of ...

Page 180

Table 67. Status codes for Master Receiver Mode Status Code (TWSR) Status of the Two-wire Serial Prescaler Bits Bus and Two-wire Serial Inter- are 0 face Hardware 0x08 A START condition has been transmitted 0x10 A repeated START condition has ...

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Slave Receiver Mode 2486O–AVR–10/04 Figure 81. Formats and States in the Master Receiver Mode MR Successfull S SLA R A reception from a slave receiver $08 $40 Next transfer started with a repeated start condition Not acknowledge A received after ...

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ATmega8(L) 182 The upper 7 bits are the address to which the Two-wire Serial Interface will respond when addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ...

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Table 68. Status Codes for Slave Receiver Mode Status Code (TWSR) Status of the Two-wire Serial Bus Prescaler Bits and Two-wire Serial Interface are 0 Hardware 0x60 Own SLA+W has been received; ACK has been returned 0x68 Arbitration lost in ...

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ATmega8(L) 184 Figure 83. Formats and States in the Slave Receiver Mode Reception of the own S SLA W slave address and one or more data bytes. All are acknowledged Last data byte received is not acknowledged Arbitration lost as ...

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Slave Transmitter Mode 2486O–AVR–10/04 In the Slave Transmitter mode, a number of data bytes are transmitted to a Master Receiver (see Figure 84). All the status codes mentioned in this section assume that the prescaler bits are zero or are ...

Page 186

Table 69. Status Codes for Slave Transmitter Mode Status Code (TWSR) Status of the Two-wire Serial Bus Prescaler Bits and Two-wire Serial Interface are 0 Hardware 0xA8 Own SLA+R has been received; ACK has been returned 0xB0 Arbitration lost in ...

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Miscellaneous States Table 70. Miscellaneous States Status Code (TWSR) Status of the Two-wire Serial Prescaler Bits Bus and Two-wire Serial Inter- are 0 face Hardware 0xF8 No relevant state information available; TWINT = “0” 0x00 Bus error due to an ...

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Combining Several TWI Modes Multi-master Systems and Arbitration ATmega8(L) 188 In some cases, several TWI modes must be combined in order to complete the desired action. Consider for example reading data from a serial EEPROM. Typically, such a transfer involves ...

Page 189

Two or more masters are performing identical communication with the same Slave. In this case, neither the Slave nor any of the masters will know about the bus contention. • Two or more masters are accessing the same ...

Page 190

Analog Comparator Special Function IO Register – SFIOR ATmega8(L) 190 The Analog Comparator compares the input values on the positive pin AIN0 and nega- tive pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage ...

Page 191

Analog Comparator Control and Status Register – ACSR 2486O–AVR–10/04 Bit ACD ACBG ACO Read/Write R/W R/W R Initial Value 0 0 N/A • Bit 7 – ACD: Analog Comparator Disable When this bit is written logic one, ...

Page 192

Analog Comparator Multiplexed Input ATmega8(L) 192 When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be dis- abled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed. It ...

Page 193

Analog-to-Digital Converter Features 2486O–AVR–10/04 • 10-bit Resolution • 0.5 LSB Integral Non-linearity • ± 2 LSB Absolute Accuracy • 260 µs Conversion Time • kSPS at Maximum Resolution • 6 Multiplexed Single Ended Input Channels ...

Page 194

ATmega8(L) 194 Figure 90. Analog to Digital Converter Block Schematic Operation 8-BIT DATA BUS ADC MULTIPLEXER SELECT (ADMUX) MUX DECODER AVCC INTERNAL 2.56V REFERENCE AREF GND BANDGAP REFERENCE ADC7 ADC6 INPUT ADC5 MUX ADC4 ADC3 ADC2 ADC1 ADC0 The ADC ...

Page 195

Starting a Conversion Prescaling and Conversion Timing 2486O–AVR–10/04 If the result is left adjusted and no more than 8-bit precision is required sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the ...

Page 196

ATmega8(L) 196 takes 13 ADC clock cycles. The first conversion after the ADC is switched on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry. The actual sample-and-hold takes place 1.5 ADC ...

Page 197

Changing Channel or Reference Selection 2486O–AVR–10/04 Figure 94. ADC Timing Diagram, Free Running Conversion One Conversion 11 Cycle Number ADC Clock ADSC ADIF ADCH ADCL Conversion Complete Table 73. ADC Conversion Time Condition Extended conversion Normal conversions, single ended The ...

Page 198

ADC Input Channels ADC Voltage Reference ADC Noise Canceler ATmega8(L) 198 When changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: In Single Conversion mode, always select the channel before starting ...

Page 199

Analog Input Circuitry Analog Noise Canceling Techniques 2486O–AVR–10/04 The analog input circuitry for single ended channels is illustrated in Figure 95. An analog source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regardless ...

Page 200

ADC Accuracy Definitions ATmega8(L) 200 Figure 96. ADC Power Connections An n-bit single-ended ADC converts a voltage linearly between GND and V steps (LSBs). The lowest code is read as 0, and the highest code is read as 2 Several ...