ATMEGA8L-8PU Atmel, ATMEGA8L-8PU Datasheet - Page 235
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ATMEGA8L-8PU
Manufacturer Part Number
ATMEGA8L-8PU
Description
IC AVR MCU 8K 8MHZ 3V 28DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets
1.ATMEGA8L-8MU.pdf
(25 pages)
2.ATMEGA8L-8MU.pdf
(302 pages)
3.ATMEGA8-16PU.pdf
(305 pages)
Specifications of ATMEGA8L-8PU
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
8MHz
Interface Type
SPI/TWI/USART
Total Internal Ram Size
1KB
# I/os (max)
23
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
6-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Through Hole
Pin Count
28
Package Type
PDIP
Processor Series
ATMEGA8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
Controller Family/series
AVR MEGA
No. Of I/o's
23
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
8MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA8L-8PU
Manufacturer:
BROADCOM
Quantity:
101
Company:
Part Number:
ATMEGA8L-8PU
Manufacturer:
ATMEL
Quantity:
33 600
Part Number:
ATMEGA8L-8PU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATMEGA8L-8PU-QS096
Manufacturer:
ATMEL
Quantity:
56
Serial Programming
Algorithm
Data Polling Flash
2486O–AVR–10/04
When writing serial data to the ATmega8, data is clocked on the rising edge of SCK.
When reading data from the ATmega8, data is clocked on the falling edge of SCK. See
Figure 113 for timing details.
To program and verify the ATmega8 in the Serial Programming mode, the following
sequence is recommended (See four byte instruction formats in Table 98):
1. Power-up sequence:
2. Wait for at least 20 ms and enable Serial Programming by sending the Program-
3. The Serial Programming instructions will not work if the communication is out of
4. The Flash is programmed one page at a time. The page size is found in Table 89
5. The EEPROM array is programmed one byte at a time by supplying the address
6. Any memory location can be verified by using the Read instruction which returns
7. At the end of the programming session, RESET can be set high to commence
8. Power-off sequence (if needed):
When a page is being programmed into the Flash, reading an address location within
the page being programmed will give the value 0xFF. At the time the device is ready for
a new page, the programmed value will read correctly. This is used to determine when
the next page can be written. Note that the entire page is written simultaneously and any
address within the page can be used for polling. Data polling of the Flash will not work
for the value 0xFF, so when programming this value, the user will have to wait for at
least t
Apply power between V
some systems, the programmer can not guarantee that SCK is held low during
Power-up. In this case, RESET must be given a positive pulse of at least two
CPU clock cycles duration after SCK has been set to “0”.
ming Enable serial instruction to pin MOSI.
synchronization. When in sync. the second byte (0x53), will echo back when
issuing the third byte of the Programming Enable instruction. Whether the echo
is correct or not, all four bytes of the instruction must be transmitted. If the 0x53
did not echo back, give RESET a positive pulse and issue a new Programming
Enable command.
on page 222. The memory page is loaded one byte at a time by supplying the 5
LSB of the address and data together with the Load Program memory Page
instruction. To ensure correct loading of the page, the data Low byte must be
loaded before data High byte is applied for a given address. The Program mem-
ory Page is stored by loading the Write Program memory Page instruction with
the 7 MSB of the address. If polling is not used, the user must wait at least
t
Note: If other commands than polling (read) are applied before any write operation
(FLASH, EEPROM, Lock Bits, Fuses) is completed, it may result in incorrect
programming.
and data together with the appropriate Write instruction. An EEPROM memory
location is first automatically erased before new data is written. If polling is not
used, the user must wait at least t
Table 97 on page 236). In a chip erased device, no 0xFFs in the data file(s) need
to be programmed.
the content at the selected address at serial output MISO.
normal operation.
Set RESET to “1”.
Turn V
WD_FLASH
WD_FLASH
CC
power off
before issuing the next page. (See Table 97).
before programming the next page. As a chip-erased device contains
CC
and GND while RESET and SCK are set to “0”. In
WD_EEPROM
before issuing the next byte. (See
ATmega8(L)
235