ATMEGA8L-8PU Atmel, ATMEGA8L-8PU Datasheet - Page 107

IC AVR MCU 8K 8MHZ 3V 28DIP

ATMEGA8L-8PU

Manufacturer Part Number
ATMEGA8L-8PU
Description
IC AVR MCU 8K 8MHZ 3V 28DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA8L-8PU

Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
8MHz
Interface Type
SPI/TWI/USART
Total Internal Ram Size
1KB
# I/os (max)
23
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
6-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Through Hole
Pin Count
28
Package Type
PDIP
Processor Series
ATMEGA8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
Controller Family/series
AVR MEGA
No. Of I/o's
23
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
8MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Compare Match Output
Unit
2486O–AVR–10/04
The Compare Output mode (COM21:0) bits have two functions. The waveform genera-
tor uses the COM21:0 bits for defining the Output Compare (OC2) state at the next
Compare Match. Also, the COM21:0 bits control the OC2 pin output source. Figure 48
shows a simplified schematic of the logic affected by the COM21:0 bit setting. The I/O
Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the
general I/O Port Control Registers (DDR and PORT) that are affected by the COM21:0
bits are shown. When referring to the OC2 state, the reference is for the internal OC2
Register, not the OC2 pin.
Figure 48. Compare Match Output Unit, Schematic
The general I/O port function is overridden by the Output Compare (OC2) from the
waveform generator if either of the COM21:0 bits are set. However, the OC2 pin direc-
tion (input or output) is still controlled by the Data Direction Register (DDR) for the port
pin. The Data Direction Register bit for the OC2 pin (DDR_OC2) must be set as output
before the OC2 value is visible on the pin. The port override function is independent of
the Waveform Generation mode.
The design of the Output Compare Pin logic allows initialization of the OC2 state before
the output is enabled. Note that some COM21:0 bit settings are reserved for certain
modes of operation. See “8-bit Timer/Counter Register Description” on page 115.
COMn1
COMn0
FOCn
clk
I/O
Waveform
Generator
D
D
D
PORT
DDR
OCn
Q
Q
Q
1
0
ATmega8(L)
OCn
Pin
107

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