ATMEGA8L-8PU Atmel, ATMEGA8L-8PU Datasheet - Page 80

• Manufacturer Part Number: ATMEGA8L-8PU
• Description: IC AVR MCU 8K 8MHZ 3V 28DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8L-8PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SPI/TWI/USART
• Total Internal Ram Size: 1KB
• # I/os (max): 23
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 6-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 28
• Package Type: PDIP
• Processor Series: ATMEGA8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AVR MEGA
• No. Of I/o's: 23
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Timer/Counter Clock
Sources
Counter Unit
80
ATmega8(L)
The Timer/Counter can be clocked by an internal or an external clock source. The clock
source is selected by the clock select logic which is controlled by the clock select
(CS12:0) bits located in the Timer/Counter Control Register B (TCCR1B). For details on
clock sources and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on
page 72.
The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional
counter unit. Figure 33 shows a block diagram of the counter and its surroundings.
Figure 33. Counter Unit Block Diagram
Signal description (internal signals):
The 16-bit counter is mapped into two 8-bit I/O memory locations: counter high
(TCNT1H) containing the upper eight bits of the counter, and Counter Low (TCNT1L)
containing the lower eight bits. The TCNT1H Register can only be indirectly accessed
by the CPU. When the CPU does an access to the TCNT1H I/O location, the CPU
accesses the High byte temporary register (TEMP). The temporary register is updated
with the TCNT1H value when the TCNT1L is read, and TCNT1H is updated with the
temporary register value when TCNT1L is written. This allows the CPU to read or write
the entire 16-bit counter value within one clock cycle via the 8-bit data bus. It is impor-
tant to notice that there are special cases of writing to the TCNT1 Register when the
counter is counting that will give unpredictable results. The special cases are described
in the sections where they are of importance.
Depending on the mode of operation used, the counter is cleared, incremented, or dec-
remented at each timer clock (clk
internal clock source, selected by the clock select bits (CS12:0). When no clock source
is selected (CS12:0 = 0) the timer is stopped. However, the TCNT1 value can be
accessed by the CPU, independent of whether clk
rides (has priority over) all counter clear or count operations.
count
direction
clear
clk
TOP
BOTTOM
T
TCNTnH (8-bit) TCNTnL (8-bit)
1
TEMP (8-bit)
DATA BUS
TCNTn (16-bit Counter)
Increment or decrement TCNT1 by 1.
Select between increment and decrement.
Clear TCNT1 (set all bits to zero).
Timer/Counter clock.
Signalize that TCNT1 has reached maximum value.
Signalize that TCNT1 has reached minimum value (zero).
(8-bit)
direction
count
T
clear
1
). The clk
Control Logic
TOP
T
1
BOTTOM
can be generated from an external or
T
1
TOVn
(Int. Req.)
clk
is present or not. A CPU write over-
Tn
( From Prescaler )
Clock Select
Detector
Edge
2486O–AVR–10/04
Tn