ATMEGA8L-8PU Atmel, ATMEGA8L-8PU Datasheet - Page 131
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ATMEGA8L-8PU
Manufacturer Part Number
ATMEGA8L-8PU
Description
IC AVR MCU 8K 8MHZ 3V 28DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets
1.ATMEGA8L-8MU.pdf
(25 pages)
2.ATMEGA8L-8MU.pdf
(302 pages)
3.ATMEGA8-16PU.pdf
(305 pages)
Specifications of ATMEGA8L-8PU
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
8MHz
Interface Type
SPI/TWI/USART
Total Internal Ram Size
1KB
# I/os (max)
23
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
6-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Through Hole
Pin Count
28
Package Type
PDIP
Processor Series
ATMEGA8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
Controller Family/series
AVR MEGA
No. Of I/o's
23
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
8MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA8L-8PU
Manufacturer:
BROADCOM
Quantity:
101
Company:
Part Number:
ATMEGA8L-8PU
Manufacturer:
ATMEL
Quantity:
33 600
Part Number:
ATMEGA8L-8PU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATMEGA8L-8PU-QS096
Manufacturer:
ATMEL
Quantity:
56
AVR USART vs. AVR UART –
Compatibility
Clock Generation
2486O–AVR–10/04
The dashed boxes in the block diagram separate the three main parts of the USART
(listed from the top): Clock generator, Transmitter and Receiver. Control Registers are
shared by all units. The clock generation logic consists of synchronization logic for exter-
nal clock input used by synchronous slave operation, and the baud rate generator. The
XCK (transfer clock) pin is only used by synchronous transfer mode. The Transmitter
consists of a single write buffer, a serial Shift Register, Parity Generator and control
logic for handling different serial frame formats. The write buffer allows a continuous
transfer of data without any delay between frames. The Receiver is the most complex
part of the USART module due to its clock and data recovery units. The recovery units
are used for asynchronous data reception. In addition to the recovery units, the Receiver
includes a parity checker, control logic, a Shift Register and a two level receive buffer
(UDR). The Receiver supports the same frame formats as the Transmitter, and can
detect Frame Error, Data OverRun and Parity Errors.
The USART is fully compatible with the AVR UART regarding:
•
•
•
•
•
However, the receive buffering has two improvements that will affect the compatibility in
some special cases:
•
•
The following control bits have changed name, but have same functionality and register
location:
•
•
The clock generation logic generates the base clock for the Transmitter and Receiver.
The USART supports four modes of clock operation: normal asynchronous, double
speed asynchronous, Master synchronous and Slave Synchronous mode. The UMSEL
bit in USART Control and Status Register C (UCSRC) selects between asynchronous
and synchronous operation. Double speed (Asynchronous mode only) is controlled by
the U2X found in the UCSRA Register. When using Synchronous mode (UMSEL = 1),
the Data Direction Register for the XCK pin (DDR_XCK) controls whether the clock
source is internal (Master mode) or external (Slave mode). The XCK pin is only active
when using Synchronous mode.
Figure 62 shows a block diagram of the clock generation logic.
Bit locations inside all USART Registers.
Baud Rate Generation.
Transmitter Operation.
Transmit Buffer Functionality.
Receiver Operation.
A second Buffer Register has been added. The two Buffer Registers operate as a
circular FIFO buffer. Therefore the UDR must only be read once for each incoming
data! More important is the fact that the Error Flags (FE and DOR) and the ninth
data bit (RXB8) are buffered with the data in the receive buffer. Therefore the status
bits must always be read before the UDR Register is read. Otherwise the error
status will be lost since the buffer state is lost.
The Receiver Shift Register can now act as a third buffer level. This is done by
allowing the received data to remain in the serial Shift Register (see Figure 61) if the
Buffer Registers are full, until a new start bit is detected. The USART is therefore
more resistant to Data OverRun (DOR) error conditions.
CHR9 is changed to UCSZ2.
OR is changed to DOR.
ATmega8(L)
131