ATMEGA8L-8PU Atmel, ATMEGA8L-8PU Datasheet - Page 72
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ATMEGA8L-8PU
Manufacturer Part Number
ATMEGA8L-8PU
Description
IC AVR MCU 8K 8MHZ 3V 28DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets
1.ATMEGA8L-8MU.pdf
(25 pages)
2.ATMEGA8L-8MU.pdf
(302 pages)
3.ATMEGA8-16PU.pdf
(305 pages)
Specifications of ATMEGA8L-8PU
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
8MHz
Interface Type
SPI/TWI/USART
Total Internal Ram Size
1KB
# I/os (max)
23
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
6-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Through Hole
Pin Count
28
Package Type
PDIP
Processor Series
ATMEGA8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
Controller Family/series
AVR MEGA
No. Of I/o's
23
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
8MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA8L-8PU
Manufacturer:
BROADCOM
Quantity:
101
Company:
Part Number:
ATMEGA8L-8PU
Manufacturer:
ATMEL
Quantity:
33 600
Part Number:
ATMEGA8L-8PU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATMEGA8L-8PU-QS096
Manufacturer:
ATMEL
Quantity:
56
Timer/Counter0 and
Timer/Counter1
Prescalers
Internal Clock Source
Prescaler Reset
External Clock Source
72
ATmega8(L)
Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the
Timer/Counters can have different prescaler settings. The description below applies to
both Timer/Counter1 and Timer/Counter0.
The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 =
1). This provides the fastest operation, with a maximum Timer/Counter clock frequency
equal to system clock frequency (f
caler can be used as a clock source. The prescaled clock has a frequency of either
f
The prescaler is free running (i.e., operates independently of the clock select logic of the
Timer/Counter) and it is shared by Timer/Counter1 and Timer/Counter0. Since the pres-
caler is not affected by the Timer/Counter’s clock select, the state of the prescaler will
have implications for situations where a prescaled clock is used. One example of pres-
caling artifacts occurs when the timer is enabled and clocked by the prescaler
(6 > CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to
the first count occurs can be from 1 to N+1 system clock cycles, where N equals the
prescaler divisor (8, 64, 256, or 1024).
It is possible to use the prescaler reset for synchronizing the Timer/Counter to program
execution. However, care must be taken if the other Timer/Counter that shares the
same prescaler also uses prescaling. A prescaler reset will affect the prescaler period
for all Timer/Counters it is connected to.
An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock
(clk
chronization logic. The synchronized (sampled) signal is then passed through the edge
detector. Figure 30 shows a functional equivalent block diagram of the T1/T0 synchroni-
zation and edge detector logic. The registers are clocked at the positive edge of the
internal system clock (
system clock.
The edge detector generates one clk
ative (CSn2:0 = 6) edge it detects.
Figure 30. T1/T0 Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system
clock cycles from an edge has been applied to the T1/T0 pin to the counter is updated.
Enabling and disabling of the clock input must be done when T1/T0 has been stable for
at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock
pulse is generated.
CLK_I/O
clk
Tn
T1
I/O
/clk
/8, f
T0
CLK_I/O
). The T1/T0 pin is sampled once every system clock cycle by the pin syn-
D Q
LE
/64, f
Synchronization
CLK_I/O
D Q
clk
I/O
/256, or f
). The latch is transparent in the high period of the internal
CLK_I/O
CLK_I/O
T1
/clk
). Alternatively, one of four taps from the pres-
T
/1024.
0
pulse for each positive (CSn2:0 = 7) or neg-
D Q
Edge Detector
2486O–AVR–10/04
Tn_sync
(To Clock
Select Logic)