F272-BAG-T-TR STMicroelectronics, F272-BAG-T-TR Datasheet - Page 11

• Manufacturer Part Number: F272-BAG-T-TR
• Description: MCU 16BIT 256K FLASH 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of F272-BAG-T-TR

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-TQFP, 144-VQFP
• Processor Series: ST10F27x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: ASC, CAN, I2C, SSC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

ST10F272B/ST10F272E
1
Introduction
The ST10F272B and ST10F272E devices are derivatives of the STMicroelectronics ST10
family of 16-bit single-chip CMOS microcontrollers.
These two derivatives slightly differ on the available RAM size and Analog Channel Input
number. These points will be highlighted in the corresponding chapters.
For all information that is common to the 2 derivatives, the generic ST10F272 name will be
used.
The ST10F272 combines high CPU performance (up to 32 million instructions per second)
with high peripheral functionality and enhanced I/O-capabilities. It also provides on-chip
high-speed single voltage Flash memory, on-chip high-speed RAM, and clock generation
via PLL.
ST10F272 is processed in 0.18mm CMOS technology. The MCU core and the logic is
supplied with a 5V to 1.8V on-chip voltage regulator. The part is supplied with a single 5V
supply and I/Os work at 5V.
The device is upward compatible with the ST10F269 device, with the following set of
differences:
Flash control interface is now based on STMicroelectronics third generation of stand-alone
Flash memories (M29F400 series), with an embedded Program/Erase Controller. This
completely frees up the CPU during programming or erasing the Flash.
Only one supply pin (ex DC1 in ST10F269, renamed into V18) on the QFP144 package is
used for decoupling the internally generated 1.8V core logic supply. Do not connect this pin
to 5.0V external supply. Instead, this pin should be connected to a decoupling capacitor
(ceramic type, typical value 10nF, maximum value 100nF).
The AC and DC parameters are modified due to a difference in the maximum CPU
frequency.
A new VDD pin replaces DC2 of ST10F269.
EA pin assumes a new alternate functionality: it is also used to provide a dedicated power
supply (see VSTBY) to maintain biased a portion of the XRAM (16Kbytes) when the main
Power Supply of the device (VDD and consequently the internally generated V18) is turned
off for low power mode, allowing data retention. VSTBY voltage shall be in the range 4.5-5.5
Volt, and a dedicated embedded low power voltage regulator is in charge to provide the 1.8V
for the RAM, the low-voltage section of the 32kHz oscillator and the Real Time Clock
module when not disabled. It is allowed to exceed the upper limit up to 6V for a very short
period of time during the global life of the device, and exceed the lower limit down to 4V
when RTC and 32kHz on-chip oscillator are not used.
A second SSC mapped on the XBUS is added (SSC of ST10F269 becomes here SSC0,
while the new one is referred as XSSC or simply SSC1). Note that some restrictions and
functional differences due to the XBUS peculiarities are present between the classic SSC,
and the new XSSC.
A second ASC mapped on the XBUS is added (ASC0 of ST10F269 remains ASC0, while
the new one is referred as XASC or simply as ASC1). Note that some restrictions and
functional differences due to the XBUS peculiarities are present between the classic ASC,
and the new XASC.
Introduction
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