F272-BAG-T-TR STMicroelectronics, F272-BAG-T-TR Datasheet - Page 39

• Manufacturer Part Number: F272-BAG-T-TR
• Description: MCU 16BIT 256K FLASH 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of F272-BAG-T-TR

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-TQFP, 144-VQFP
• Processor Series: ST10F27x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: ASC, CAN, I2C, SSC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

ST10F272B/ST10F272E
5.5.3
5.5.4
Flash non volatile access protection register 0
FNVAPR0 (0x08 DFB8)
Table 20.
Flash non volatile access protection register 1 low
FNVAPR1L (0x08 DFBC)
Table 21.
PDS15 PDS14 PDS13 PDS12 PDS11 PDS10 PDS9 PDS8 PDS7 PDS6 PDS5 PDS4 PDS3 PDS2 PDS1 PDS0
ACCP
DBGP
PDS(15:0)
RW
15
15
Bit
Bit
RW
14
14
RW
13
13
Flash non volatile access protection register 0
Flash non volatile access protection register 1 low
Access Protection
This bit, if programmed at 0, disables any access (read/write) to data mapped
inside IFlash Module address space, unless the current instruction is fetched from
IFlash.
Debug Protection
This bit, if erased at 1, allows to by-pass all the protections using the Debug
features through the Test Interface. If programmed at 0, on the contrary, all the
debug features, the Test Interface and all the Flash Test Modes are disabled. Even
STMicroelectronics will not be able to access the device to run any eventual failure
analysis.
Protections Disable 15-0
If bit PDSx is programmed at 0 and bit PENx is erased at 1, the action of bit ACCP
is disabled. Bit PDS0 can be programmed at 0 only if both bits DBGP and ACCP
have already been programmed at 0. Bit PDSx can be programmed at 0 only if bit
PENx-1 has already been programmed at 0.
RW
12
12
RW
11
11
RW
10
10
RW
reserved
9
9
NVR
NVR
RW
8
8
RW
7
7
Function
Function
RW
6
6
RW
5
5
RW
4
4
Internal Flash memory
RW
3
Delivery value:: FFFFh
3
Reset value: ACFFh
RW
2
2
DBGP ACCP
RW
RW
1
1
39/182
RW
RW
0
0