F272-BAG-T-TR STMicroelectronics, F272-BAG-T-TR Datasheet - Page 57

• Manufacturer Part Number: F272-BAG-T-TR
• Description: MCU 16BIT 256K FLASH 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of F272-BAG-T-TR

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-TQFP, 144-VQFP
• Processor Series: ST10F27x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: ASC, CAN, I2C, SSC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

ST10F272B/ST10F272E
available vector. If more than one source is enabled to issue the request, the service routine
will have to take care to identify the real event to be serviced. This can easily be done by
checking the flag bits (Byte Low of XIRxSEL register). Note that the flag bits can also
provide information about events which are not currently serviced by the interrupt controller
(since masked through the enable bits), allowing an effective software management also in
absence of the possibility to serve the related interrupt request: a periodic polling of the flag
bits may be implemented inside the user application.
Figure 9.
The
four X-interrupt vectors.
Table 29.
CAN1 Interrupt
CAN2 Interrupt
I2C Receive
I2C Transmit
I2C Error
SSC1 Receive
SSC1 Transmit
SSC1 Error
ASC1 Receive
ASC1 Transmit
ASC1 Transmit Buffer
Table 29
IT Source 7
IT Source 6
IT Source 5
IT Source 4
IT Source 3
IT Source 2
IT Source 1
IT Source 0
X-Interrupt basic structure
X-Interrupt detailed mapping
summarizes the mapping of the different interrupt sources which shares the
15
7
Enable[7:0]
Flag[7:0]
0
8
XIRxSEL[7:0] (x = 0, 1, 2, 3)
XIRxSEL[15:8] (x = 0, 1, 2, 3)
XP0INT
x
x
x
x
x
x
x
x
XP1INT
x
x
x
x
x
x
x
x
XPxIC.XPxIR (x = 0, 1, 2, 3)
XP2INT
x
x
x
x
x
x
x
Interrupt system
XP3INT
x
x
x
x
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