F272-BAG-T-TR STMicroelectronics, F272-BAG-T-TR Datasheet - Page 44

• Manufacturer Part Number: F272-BAG-T-TR
• Description: MCU 16BIT 256K FLASH 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of F272-BAG-T-TR

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-TQFP, 144-VQFP
• Processor Series: ST10F27x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: ASC, CAN, I2C, SSC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Internal Flash memory
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A Sector Erase can be suspended by setting SUSP bit.
●
●
●
Set protection
Example 1: Enable Write Protection of sectors B0F3-0 of Bank 0 in IFLASH module.
Example 2: Enable Access and Debug Protection.
Example 3: Disable in a permanent way Access and Debug Protection.
Example 4: Enable again in a permanent way Access and Debug Protection, after having
disabled them.
PEN0*/
Disable and re-enable of Access and Debug Protection in a permanent way (as shown by
examples 3 and 4) can be done for a maximum of 16 times.
FCR0H
FARL
FARH
FDR0L
FDR0H
FCR0H
FCR0H
FARL
FARH
FDR0L
FCR0H
XFVTAUR0
FCR0H
FARL
FARH
FDR0L
FCR0H
XFVTAUR0
FCR0H
FARL
FARH
FDR0H
FCR0H
XFVTAUR0 = 0x0000;
To perform a Word Program operation during Erase Suspend, firstly bits SUSP and
SER must be reset, then bit WPG and WMS can be set.
To resume the Sector Erase operation bit SER must be set again.
In any case it is forbidden to start any write operation with SUSP bit already set.
|= 0x0100;
|= 0x8000;
|= 0x0100;
|= 0x8000;
= 0xDFB4;
= 0x0008;
= 0xFFF0;
= 0xFFFF;
= 0xDFB8;
= 0x0008;
= 0xFFFC;
|= 0x0100;
|= 0x8000;
|= 0x0100;
|= 0x8000;
= 0x0001;
= 0xDFBC;
= 0x0008;
= 0xFFFE;
= 0x0001;
= 0xDFBC;
= 0x0008;
= 0xFFFE;
/*Set SPR in FCR0H*/
/*Load Add of register FNVWPIR in FARL*/
/*Load Add of register FNVWPIR in FARH*/
/*Load Data in FDR0L*/
/*Load Data in FDR0H*/
/*Operation start*/
/*Set SPR in FCR0H*/
/*Load Add of register FNVAPR0 in FARL*/
/*Load Add of register FNVAPR0 in FARH*/
/*Load Data in FDR0L*/
/*Operation start*/
/*Set TAUB in XFVTAUR0*/
/*Set SPR in FCR0H*/
/*Load Add of register FNVAPR1L in FARL*/
/*Load Add of register FNVAPR1L in FARH*/
/*Load Data in FDR0L for clearing PDS0*/
/*Operation start*/
/*Set TAUB in XFVTAUR0*/
/*Set SPR in FCR0H*/
/*Load Add register FNVAPR1H in FARL*/
/*Load Add register FNVAPR1H in FARH*/
/*Load Data in FDR0H for clearing
/*Operation start*/
/*Reset TAUB in XFVTAUR0*/
ST10F272B/ST10F272E