F272-BAG-T-TR STMicroelectronics, F272-BAG-T-TR Datasheet - Page 174

• Manufacturer Part Number: F272-BAG-T-TR
• Description: MCU 16BIT 256K FLASH 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of F272-BAG-T-TR

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-TQFP, 144-VQFP
• Processor Series: ST10F27x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: ASC, CAN, I2C, SSC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Electrical characteristics
24.8.20
24.8.20.1 Master mode
Table 81.
1. Maximum Baudrate is in reality 8Mbaud, that can be reached with 64MHz CPU clock and <SSCBR> set to ‘3h’, or with
2. Formula for SSC Clock Cycle time: t
3. Partially tested, guaranteed by design characterization.
174/182
t
t
t
t
t
t
t
t
t
t
t
300
301
302
303
304
305
306
307p
308p
307
308
Symbol
48MHz CPU clock and <SSCBR> set to ‘2h’. When 40MHz CPU clock is used the maximum baudrate cannot be higher
than 6.6Mbaud (<SSCBR> = ‘2h’) due to the limited granularity of <SSCBR>. Value ‘1h’ for <SSCBR> can be used only
with CPU clock equal to (or lower than) 32MHz.
Baudrate register, taken as unsigned 16-bit integer. Minimum limit allowed for t
CC SSC clock cycle time
CC SSC clock high time
CC SSC clock low time
CC SSC clock rise time
CC SSC clock fall time
CC Write data valid after shift edge
CC Write data hold after shift edge
SR
SR
SR
SR
High-speed synchronous serial interface (SSC) timing
V
SSC master mode timings
Read data setup time before latch
edge, phase error detection on
(SSCPEN = 1)
Read data hold time after latch
edge, phase error detection on
(SSCPEN = 1)
Read data setup time before latch
edge, phase error detection off
(SSCPEN = 0)
Read data hold time after latch
edge, phase error detection off
(SSCPEN = 0)
DD
= 5V ±10%, V
Parameter
SS
300
(2))
= 0V, T
= 4 TCL x (<SSCBR> + 1) Where <SSCBR> represents the content of the SSC
(3)
A
= -40 to +125°C, C
Max. Baudrate 6.6MBd
(1)
(<SSCBR> = 0002h)
@F
min.
37.5
150
– 2
63
63
50
25
CPU
–
–
–
0
= 40MHz
L
max.
150
= 50pF
10
10
15
–
–
–
–
–
–
–
300
is 125ns (corresponding to 8Mbaud).
2TCL + 12.5
t
t
300
300
(<SSCBR> = 0001h -
8TCL
4TCL
2TCL
min.
Variable Baudrate
/ 2 – 12
/ 2 – 12
– 2
–
–
–
0
ST10F272B/ST10F272E
FFFFh)
262144 TCL
max.
10
10
15
–
–
–
–
–
–
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns