F272-BAG-T-TR STMicroelectronics, F272-BAG-T-TR Datasheet - Page 31

• Manufacturer Part Number: F272-BAG-T-TR
• Description: MCU 16BIT 256K FLASH 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of F272-BAG-T-TR

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-TQFP, 144-VQFP
• Processor Series: ST10F27x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: ASC, CAN, I2C, SSC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

ST10F272B/ST10F272E
5.4
5.4.1
Registers description
Flash control register 0 low
The Flash Control Register 0 Low (FCR0L) together with the Flash Control Register 0 High
(FCR0H) is used to enable and to monitor all the write operations on the IFLASH. The user
has no access in write mode to the Test-Flash (B0TF). Besides, Test-Flash block is seen by
the user in Bootstrap Mode only.
FCR0L (0x08 0000)
Table 7.
BSY0
LOCK
15
Bit
14
Flash control register 0 low
13
Bank 0 Busy (IFLASH)
This bit indicates that a write operation is running on Bank 0 (IFLASH). It is
automatically set when bit WMS is set. Setting Protection operation sets bit BSY0
(since protection registers are in this Block). When this bit is set, every read
access to Bank 0 will output invalid data (software trap 009Bh), while every write
access to the Bank will be ignored. At the end of the write operation or during a
Program or Erase Suspend this bit is automatically reset and the Bank returns to
read mode. After a Program or Erase Resume this bit is automatically set again.
Flash Registers Access Locked
When this bit is set, it means that the access to the Flash Control Registers
FCR0H/-FCR1H/L, FDR0H/L-FDR1H/L, FARH/L and FER is locked by the FPEC:
any read access to the registers will output invalid data (software trap 009Bh) and
any write access will be ineffective. LOCK bit is automatically set when the Flash
bit WMS is set.
This is the only bit the user can always access to detect the status of the Flash:
once it is found low, the rest of FCR0L and all the other Flash registers are
accessible by the user as well.
Note that FER content can be read when LOCK is low, but its content is updated
only when also BSY0 bit is reset.
12
11
reserved
10
9
FCR
8
7
Function
6
5
LOCK
R
4
Internal Flash memory
res.
3
Reset Value: 0000h
res.
2
BSY0
R
1
31/182
res.
0
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