F272-BAG-T-TR STMicroelectronics, F272-BAG-T-TR Datasheet - Page 158

• Manufacturer Part Number: F272-BAG-T-TR
• Description: MCU 16BIT 256K FLASH 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of F272-BAG-T-TR

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-TQFP, 144-VQFP
• Processor Series: ST10F27x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: ASC, CAN, I2C, SSC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Electrical characteristics
24.8.16
Table 77.
158/182
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
22
23
25
27
38
Symbol
CC
CC
CC
CC
CC
CC
CC
CC
CC
SR
SR
SR
SR
SR
SR
CC
CC
CC
CC
CC
Multiplexed bus
V
ALE cycle time = 6 TCL + 2t
Multiplexed bus timings
ALE high time
Address setup to ALE
Address hold after ALE
ALE falling edge to RD, WR
(with RW-delay)
ALE falling edge to RD, WR
(no RW-delay)
Address float after RD, WR
(with
Address float after RD, WR
(no
RD, WR low time
(with RW-delay)
RD, WR low time
RD to valid data in
RD to valid data in
ALE low to valid data in
Address/Unlatched CS to valid
data in
Data hold after RD
rising edge
Data float after
Data valid to WR
Data hold after WR
ALE rising edge after RD, WR
Address/Unlatched CS hold
after RD, WR
ALE falling edge to Latched CS
(no RW-delay)
(with RW-delay)
(no RW-delay)
DD
RW-delay)1
= 5V ± 10%, V
RW-delay)1
Parameter
RD1
SS
= 0V, T
A
A
– 8.5 + t
+ t
15.5 + t
1.5 + t
– 4 – t
28 + t
10 + t
= –40 to +125°C, CL = 50pF,
15 + t
10 + t
4 + t
4 + t
4 + t
4 + t
min.
C
F
–
–
–
–
–
–
0
–
TCL = 12.5 ns
+ t
CPU
A
A
A
F
C
C
F
F
A
A
C
F
A
= 40 MHz
(75ns at 40MHz CPU clock without wait states)
20 + 2t
18.5 + t
16.5 + t
+ t
10 – t
17.5 +
6 + t
max.
18.5
+ t
A
–
–
–
–
–
6
–
–
–
–
–
–
–
+ t
C
C
A
A
C
C
F
+
2TCL – 9.5 + t
3TCL – 9.5 + t
2TCL – 8.5 + t
2TCL – 15 + t
2TCL – 10 + t
2TCL – 15 + t
TCL – 8.5 + t
TCL – 8.5 + t
TCL – 8.5 + t
TCL – 11 + t
– 8.5 + t
– 4 – t
min.
1/2 TCL = 1 to 64MHz
Variable CPU Clock
–
–
–
–
–
–
0
–
A
A
A
A
A
A
C
F
F
C
C
ST10F272B/ST10F272E
F
2TCL – 8.5 + t
2TCL – 19 + t
3TCL – 19 + t
3TCL – 20 +
4TCL – 30 +
+ 2t
TCL + 6
+ t
10 – t
max.
A
A
–
–
–
–
–
6
–
–
–
–
–
–
–
+ t
+ t
A
C
C
C
C
F
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns