F272-BAG-T-TR STMicroelectronics, F272-BAG-T-TR Datasheet - Page 143

• Manufacturer Part Number: F272-BAG-T-TR
• Description: MCU 16BIT 256K FLASH 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of F272-BAG-T-TR

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-TQFP, 144-VQFP
• Processor Series: ST10F27x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: ASC, CAN, I2C, SSC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

ST10F272B/ST10F272E
The formula above provides a constraints for external network design, in particular on
resistive path.
A second aspect involving the capacitance network shall be considered. Assuming the three
capacitances C
equivalent circuit reported in Figure 40), when the sampling phase is started (A/D switch
close), a charge sharing phenomena is installed.
Figure 41. Charge sharing timing diagram during sampling phase
In particular two different transient periods can be distinguished (see Figure 41):
●
●
A first and quick charge transfer from the internal capacitance C
sampling capacitance C
considering a worst case (since the time constant in reality would be faster) in which
C
are in series, and the time constant is:
This relation can again be simplified considering only C
condition. In reality, the transient is faster, but the A/D Converter circuitry has been
designed to be robust also in the very worst case: the sampling time T
longer than the internal time constant:
The charge of C
voltage V
A second charge transfer involves also C
capacitance) through the resistance R
and C
time constant is:
In this case, the time constant depends on the external circuit: in particular imposing
that the transient is completed well before the end of sampling time T
P2
is reported in parallel to C
V
S
V
V
V
CS
A
A2
A1
were in parallel to C
A1
F
1
, C
on the capacitance according to the following equation:
P1
P1
Voltage Transient on C
and C
V A1
and C
τ 1
P2
⋅
2
S
<
P2
(
initially charged at the source voltage V
occurs (C
C S
τ 1
(
R SW
τ 2
P1
is redistributed also on C
=
+
P1
<
(since the time constant in reality would be faster), the
C P1
(
R L
R SW
(call C
+
R AD
⋅
S
+
(
S
is supposed initially completely discharged):
C P2
+
C S
L
: again considering the worst case in which C
)
P
R AD
T
⋅
= C
F
+
S
)
C S
(that is typically bigger than the on-chip
C P1
=
)
P1
∆V < 0.5 LSB
⋅
t
< <
V A
C P
----------------------- -
C P
+ C
+
⋅
C P2
⋅
T
+
P2
(
S
C P1
C S
C S
S
), the two capacitance C
τ
τ
)
, determining a new value of the
1
2
S
< (R
= R
+
as an additional worst
C P2
L
SW
Electrical characteristics
(C
)
S
+ R
P1
+ C
A
AD
and C
(refer to the
P1
S
) C
S
, a constraints on
+ C
is always much
S
<< T
P2
P2
)
to the
S
P
and C
143/182
P2
S