F272-BAG-T-TR STMicroelectronics, F272-BAG-T-TR Datasheet - Page 175

• Manufacturer Part Number: F272-BAG-T-TR
• Description: MCU 16BIT 256K FLASH 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of F272-BAG-T-TR

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-TQFP, 144-VQFP
• Processor Series: ST10F27x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: ASC, CAN, I2C, SSC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

ST10F272B/ST10F272E
24.8.20.2 Slave mode
Table 82.
t
t
t
t
t
t
t
t
t
310
311
312
313
314
315
316
317p
318p
Symbol
CC Write data valid after shift edge
CC Write data hold after shift edge
SR SSC clock cycle time
SR SSC clock high time
SR SSC clock low time
SR SSC clock rise time
SR SSC clock fall time
SR
SR
Figure 61. SSC master timing
1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock
2. The bit timing is repeated for all bits to be transmitted or received.
V
SSC slave mode timings
Read data setup time before latch
edge, phase error detection on
(SSCPEN = 1)
Read data hold time after latch
edge, phase error detection on
(SSCPEN = 1)
DD
SCLK
MTSR
MRST
edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading
clock edge is low-to-high transition (SSCPO = 0b).
= 5V ±10%, V
Parameter
1)
t
SS
305
(2)
t
1st in bit
307
= 0V, T
1st out bit
t
300
t
308
A
= -40 to +125°C, C
t
305
t
301
t
304
(<SSCBR> = 0002h)
min.
2nd out bit
150
@F
63
63
62
87
Max. Baudrate
–
–
–
0
2nd In bit
t
302
6.6 MBd
CPU
= 40MHz
t
303
(1)
t
306
L
max.
150
)
10
10
55
= 50pF
–
–
–
–
–
2)
t
t
4TCL + 12
6TCL + 12
310
310
(<SSCBR> = 0001h -
t
8TCL
305
min.
Variable Baudrate
/ 2 – 12
/ 2 – 12
–
–
0
–
t
Electrical characteristics
Last in bit
307
Last out bit
FFFFh)
t
308
262144 TCL
2TCL + 30
max.
10
10
–
–
–
–
–
175/182
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns