F272-BAG-T-TR STMicroelectronics, F272-BAG-T-TR Datasheet - Page 58

• Manufacturer Part Number: F272-BAG-T-TR
• Description: MCU 16BIT 256K FLASH 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of F272-BAG-T-TR

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-TQFP, 144-VQFP
• Processor Series: ST10F27x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: ASC, CAN, I2C, SSC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Interrupt system
9.2
Note:
58/182
Table 29.
Exception and error traps list
Table 30
time.
Table 30.
* - All the class B traps have the same trap number (and vector) and the same lower priority
compare to the class A traps and to the resets.
- Each class A traps has a dedicated trap number (and vector). They are prioritized in the
second priority level.
- The resets have the highest priority level and the same trap number.
- The PSW.ILVL CPU priority is forced to the highest level (15) when these exceptions are
serviced.
ASC1 Error
PLL Unlock / OWD
PWM1 Channel 3...0
Reset Functions:
Hardware Reset
Software Reset
Watchdog Timer Overflow
Class A Hardware Traps:
Non-Maskable Interrupt
Stack Overflow
Stack Underflow
Class B Hardware Traps:
Undefined Opcode
MAC Interruption
Protected Instruction Fault
Illegal word Operand Access
Illegal Instruction Access
Illegal External Bus Access
Reserved
Software Traps
TRAP Instruction
Exception Condition
shows all of the possible exceptions or error conditions that can arise during run-
X-Interrupt detailed mapping (continued)
Trap priorities
UNDOPC
MACTRP
PRTFLT
ILLOPA
ILLBUS
STKOF
STKUF
ILLINA
Trap
Flag
NMI
XP0INT
STOTRAP
STUTRAP
NMITRAP
RESET
RESET
RESET
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
Vector
Trap
[002Ch - 003Ch]
0000h – 01FCh
XP1INT
in steps of 4h
Location
00’0000h
00’0000h
00’0000h
00’0008h
00’0010h
00’0018h
00’0028h
00’0028h
00’0028h
00’0028h
00’0028h
00’0028h
Vector
Any
ST10F272B/ST10F272E
XP2INT
[0Bh - 0Fh]
[00h - 7Fh]
x
Number
Trap
0Ah
0Ah
0Ah
0Ah
0Ah
0Ah
Any
00h
00h
00h
02h
04h
06h
XP3INT
Priority
Current
Priority
Trap*
x
CPU
x
x
III
III
III
II
II
II
I
I
I
I
I
I