F272-BAG-T-TR STMicroelectronics, F272-BAG-T-TR Datasheet - Page 63

• Manufacturer Part Number: F272-BAG-T-TR
• Description: MCU 16BIT 256K FLASH 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of F272-BAG-T-TR

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-TQFP, 144-VQFP
• Processor Series: ST10F27x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: ASC, CAN, I2C, SSC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

ST10F272B/ST10F272E
11.2
GPT2
The GPT2 module provides precise event control and time measurement. It includes two
timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an
input clock which is derived from the CPU clock via a programmable prescaler or with
external signals. The count direction (up/down) for each timer is programmable by software
or may additionally be altered dynamically by an external signal on a port pin (TxEUD).
Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6
which changes its state on each timer overflow/underflow.
The state of this latch may be used to clock timer T5, or it may be output on a port pin
(T6OUT). The overflow / underflow of timer T6 can additionally be used to clock the
CAPCOM timers T0 or T1, and to cause a reload from the CAPREL register. The CAPREL
register may capture the contents of timer T5 based on an external signal transition on the
corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the capture
procedure. This allows absolute time differences to be measured or pulse multiplication to
be performed without software overhead.
The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1
timer T3 inputs T3IN and/or T3EUD. This is advantageous when T3 operates in Incremental
Interface Mode.
Table 36
scaler option at 40MHz and 64MHz CPU clock respectively.
Table 36.
Table 37.
Pre-scaler
factor
Input Freq
Resolution
Period
maximum
Pre-scaler
factor
Input Freq
Resolution
Period
maximum
f
f
CPU
CPU
= 40MHz
= 64MHz
and
GPT2 timer input frequencies, resolutions and periods at 40 MHz
GPT2 timer input frequencies, resolutions and periods at 64 MHz
Table 37
6.55ms
10MHz
16MHz
62.5ns
100ns
4.1ms
000b
000b
4
4
list the timer input frequencies, resolution and periods for each pre-
13.1ms
200ns
125ns
8.2ms
5MHz
8MHz
001b
001b
8
8
2.5MHz
26.2ms
16.4ms
400ns
250ns
4MHz
010b
010b
16
16
Timer Input Selection T5I / T6I
Timer Input Selection T5I / T6I
52.4ms
32.8ms
2MHz
0.8µs
0.5µs
011b
011b
MHz
1.25
32
32
104.8ms 209.7ms 419.4ms
625 kHz
65.5ms
1 kHz
1.6µs
1.0µs
100b
100b
64
64
General purpose timer unit
131.1ms 262.1ms
500 kHz
312.5
3.2µs
2.0µs
101b
101b
128
kHz
128
250 kHz
156.25
6.4µs
4.0µs
110b
110b
256
kHz
256
838.9ms
524.3ms
128 kHz
78.125
12.8µs
8.0µs
111b
111b
512
kHz
512
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