F272-BAG-T-TR STMicroelectronics, F272-BAG-T-TR Datasheet - Page 49

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F272-BAG-T-TR

Manufacturer Part Number
F272-BAG-T-TR
Description
MCU 16BIT 256K FLASH 144-TQFP
Manufacturer
STMicroelectronics
Series
ST10r
Datasheet

Specifications of F272-BAG-T-TR

Core Processor
ST10
Core Size
16-Bit
Speed
40MHz
Connectivity
ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
111
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
144-TQFP, 144-VQFP
Processor Series
ST10F27x
Core
ST10
Data Bus Width
16 bit
Data Ram Size
12 KB
Interface Type
ASC, CAN, I2C, SSC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
111
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 24 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
F272-BAG-T-TR
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
F272-BAG-T-TR
Manufacturer:
ST
0
ST10F272B/ST10F272E
7.1
Multiplier-accumulator unit (MAC)
The MAC co-processor is a specialized co-processor added to the ST10 CPU Core in order
to improve the performances of the ST10 Family in signal processing algorithms.
The standard ST10 CPU has been modified to include new addressing capabilities which
enable the CPU to supply the new co-processor with up to 2 operands per instruction cycle.
This new co-processor (so-called MAC) contains a fast multiply-accumulate unit and a
repeat unit.
The co-processor instructions extend the ST10 CPU instruction set with multiply, multiply-
accumulate, 32-bit signed arithmetic operations.
Figure 8.
Note: * Shared with standard ALU
Controller
ST10 CPU
Interrupt
GPR Pointers *
IDX0 Pointer
IDX1 Pointer
QR0 GPR Offset Register
QR1 GPR Offset Register
QX0 IDX Offset Register
QX1 IDX Offset Register
MAC unit architecture
Repeat Unit
MRW
Control Unit
MCW
Concatenation
MSW
Flags MAE
32
40
0h
Sign Extend
Operand 1
Scaler
40
40
Mux
Mux
40-bit Signed Arithmetic Unit
A
signed/unsigned
16
40
08000h
Central processing unit (CPU)
Multiplier
16 x 16
32
MAH
8-bit Left/Right
16
40
40
Shifter
Operand 2
40
0h
MAL
40
Mux
B
40
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