MC9S08DZ128MLL Freescale Semiconductor, MC9S08DZ128MLL Datasheet - Page 136

• Manufacturer Part Number: MC9S08DZ128MLL
• Description: MCU 8BIT 128K FLASH 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08DZ128MLL

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Processor Series: S08DZ
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 88
• Number Of Timers: 3
• Operating Supply Voltage: 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08DZ60
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 24 Channel
• Controller Family/series: HCS08
• No. Of I/o's: 87
• Eeprom Memory Size: 2KB
• Ram Memory Size: 8KB
• Cpu Speed: 40MHz
• No. Of Timers: 3
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 6 Parallel Input/Output Control
6.5.10
Port K is controlled by the registers listed below.
6.5.10.1
6.5.10.2
136
PTKDD[7:0]
PTKD[7:0]
Reset:
Reset:
Field
Field
7:0
7:0
W
W
R
R
PTKDD7
PTKD7
Port K Registers
Port K Data Register Bits — For port K pins that are inputs, reads return the logic level on the pin. For port K
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port K pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTKD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pull-ups disabled.
Data Direction for Port K Bits — These read/write bits control the direction of port K pins and what is read for
PTKD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port K bit n and PTKD reads return the contents of PTKDn.
Port K Data Register (PTKD)
0
Port K Data Direction Register (PTKDD)
0
7
7
PTKDD6
PTKD6
0
0
6
6
Figure 6-61. Port K Data Direction Register (PTKDD)
Table 6-59. PTKDD Register Field Descriptions
Table 6-58. PTKD Register Field Descriptions
Figure 6-60. Port K Data Register (PTKD)
MC9S08DZ128 Series Data Sheet, Rev. 1
PTKDD5
PTKD5
0
0
5
5
PTKDD4
PTKD4
0
0
4
4
Description
Description
PTKDD3
PTKD3
3
0
3
0
PTKDD2
PTKD2
0
0
2
2
PTKDD1
Freescale Semiconductor
PTKD1
0
0
1
1
PTKDD0
PTKD0
0
0
0
0