MC9S08DZ128MLL Freescale Semiconductor, MC9S08DZ128MLL Datasheet - Page 414

• Manufacturer Part Number: MC9S08DZ128MLL
• Description: MCU 8BIT 128K FLASH 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08DZ128MLL

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Processor Series: S08DZ
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 88
• Number Of Timers: 3
• Operating Supply Voltage: 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08DZ60
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 24 Channel
• Controller Family/series: HCS08
• No. Of I/o's: 87
• Eeprom Memory Size: 2KB
• Ram Memory Size: 8KB
• Cpu Speed: 40MHz
• No. Of Timers: 3
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 18 Debug Module (S08DBGV3) (128K)
18.4.4.3.7
In the A And Not B trigger mode, comparator A compares to the address bus and comparator B compares
to the data bus. In the A And Not B trigger mode, if the match condition for A and Not B happen on the
same bus cycle, both the AF and BF flags in the DBGS register are set. If a match condition on only A or
only Not B occur no flags are set.
For Breakpoint tagging operation with an end-trigger type trace, only matches from Comparator A will be
used to determine if the Breakpoint conditions are met and Comparator B matches will be ignored.
18.4.4.3.8
In the Inside Range trigger mode, if the match condition for A and B happen on the same bus cycle, both
the AF and BF flags in the DBGS register are set. If a match condition on only A or only B occur no flags
are set.
18.4.4.3.9
In the Outside Range trigger mode, if the match condition for A or B is met, the corresponding flag in the
DBGS register is set.
The four control bits BEGIN and TRGSEL in DBGT, and BRKEN and TAG in DBGC, determine the basic
type of debug run as shown in Table 1.21. Some of the 16 possible combinations are not used (refer to the
notes at the end of the table).
414
BEGIN
0
0
0
0
0
0
1
1
1
1
1
1
A And Not B (Full Mode)
Inside Range, A ≤ address ≤ B
Outside Range, address < A or address > B
TRGSEL
0
0
0
1
1
1
0
0
0
1
1
1
BRKEN
0
1
1
0
1
1
0
1
1
0
1
1
Table 18-21. Basic Types of Debug Runs
MC9S08DZ128 Series Data Sheet, Rev. 1
TAG
x
x
x
x
(1)
(1)
(1)
(1)
0
1
0
1
0
1
0
1
Fill FIFO until trigger address (No CPU breakpoint - keep
running)
Fill FIFO until trigger address, then force CPU breakpoint
Do not use
Fill FIFO until trigger opcode about to execute (No CPU
breakpoint - keep running)
Do not use
Fill FIFO until trigger opcode about to execute (trigger causes
CPU breakpoint)
Start FIFO at trigger address (No CPU breakpoint - keep
running)
Start FIFO at trigger address, force CPU breakpoint when
FIFO full
Start FIFO at trigger opcode (No CPU breakpoint - keep
running)
Start FIFO at trigger opcode, force CPU breakpoint when FIFO
full
Do not use
Do not use
(2)
(3)
(4)
(4)
Type of Debug Run
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