MC9S08DZ128MLL Freescale Semiconductor, MC9S08DZ128MLL Datasheet - Page 59

• Manufacturer Part Number: MC9S08DZ128MLL
• Description: MCU 8BIT 128K FLASH 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08DZ128MLL

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Processor Series: S08DZ
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 88
• Number Of Timers: 3
• Operating Supply Voltage: 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08DZ60
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 24 Channel
• Controller Family/series: HCS08
• No. Of I/o's: 87
• Eeprom Memory Size: 2KB
• Ram Memory Size: 8KB
• Cpu Speed: 40MHz
• No. Of Timers: 3
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

0x18C7
0x18C8
0x18C9
0x18CA
0x18CB
0x18CC
0x18CD
0x18CE
0x18CF
0x18D0
0x18D1–
0x18D7
0x18D8
0x18D9
0x18DA
0x18DB
0x18DC
0x18DD
0x18DE–
0x18FF
0x18A0
0x18A1
0x18A2
0x18A3
0x18A4 –
0x18AB
0x18AC
0x18AD
0x18AE
0x18AF
0x18B0
0x18B1
0x18B2
Figure 4-4
registers vary depending on whether standard or extended mapping is selected. See
“Freescale’s Controller Area Network
mapping.
Freescale Semiconductor
Address
Table 4-4. MSCAN Foreground Receive and Transmit Buffer Layouts — Extended Mapping Shown
TPM3C0VL
TPM3C1SC
TPM3C1VH
TPM3C1VL
TPM3C2SC
TPM3C2VH
TPM3C2VL
TPM3C3SC
TPM3C3VH
TPM3C3VL
Reserved
IIC2A
IIC2F
IIC2C1
IIC2S
IIC2D
IIC2C2
Reserved
CANRIDR0
CANRIDR1
CANRIDR2
CANRIDR3
CANRDSR0 –
CANRDSR7
CANRDLR
Reserved
CANRTSRH
CANRTSRL
CANTIDR0
CANTIDR1
CANTIDR2
Register Name
shows the structure of receive and transmit buffers for extended identifier mapping. These
Table 4-3. High-Page Register Summary (Sheet 5 of 5)
GCAEN
TSR15
IICEN
CH1F
Bit 15
CH2F
Bit 15
CH3F
Bit 15
TSR7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
ID28
ID20
ID14
ID28
ID20
ID14
AD7
TCF
DB7
ID6
—
—
—
—
—
—
MULT
MC9S08DZ128 Series Data Sheet, Rev. 1
ADEXT
TSR14
CH1IE
CH2IE
CH3IE
TSR6
IICIE
IAAS
ID27
ID19
ID13
ID27
ID19
ID13
AD6
DB6
ID5
14
14
14
(S08MSCANV1),” for details on extended and standard identifier
—
—
—
—
—
—
6
6
6
6
6
(Sheet 1 of 2)
TSR13
MS1B
MS2B
MS3B
BUSY
TSR5
MST
ID26
ID18
ID12
ID26
ID18
ID12
AD5
DB5
ID4
13
13
13
—
—
—
—
—
—
5
5
5
5
5
0
SRR
SRR
TSR12
MS1A
MS2A
MS3A
ARBL
TSR4
ID25
ID11
ID25
ID11
AD4
DB4
ID3
TX
12
12
12
—
—
—
—
—
—
4
4
4
4
4
0
(1)
(3)
DATA
ELS1B
ELS2B
ELS3B
TSR11
TXAK
IDE
IDE
DLC3
TSR3
ID24
ID10
ID24
ID10
AD3
DB3
ID2
11
11
11
—
—
—
—
—
3
3
3
3
3
0
0
(1)
(1)
ICR
ELS1A
ELS2A
ELS3A
TSR10
RSTA
DLC2
TSR2
AD10
SRW
ID23
ID17
ID23
ID17
AD2
DB2
ID9
ID1
ID9
10
10
10
—
—
—
—
—
2
2
2
2
2
Chapter 12,
DLC1
TSR9
TSR1
IICIF
ID22
ID16
ID22
ID16
AD1
AD9
DB1
ID8
ID0
ID8
—
—
—
—
—
1
1
0
9
1
0
9
1
0
9
1
0
Chapter 4 Memory
RXAK
DLC0
TSR8
TSR0
RTR
Bit 0
ID21
ID15
ID21
ID15
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
AD8
DB0
ID7
ID7
—
—
—
—
—
0
0
0
0
0
2
59