MC9S08DZ128MLL Freescale Semiconductor, MC9S08DZ128MLL Datasheet - Page 311

• Manufacturer Part Number: MC9S08DZ128MLL
• Description: MCU 8BIT 128K FLASH 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08DZ128MLL

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Processor Series: S08DZ
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 88
• Number Of Timers: 3
• Operating Supply Voltage: 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08DZ60
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 24 Channel
• Controller Family/series: HCS08
• No. Of I/o's: 87
• Eeprom Memory Size: 2KB
• Ram Memory Size: 8KB
• Cpu Speed: 40MHz
• No. Of Timers: 3
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.1.3
As shown in
prescale bits (SPPR2:SPPR1:SPPR0) choose a prescale divisor of 1, 2, 3, 4, 5, 6, 7, or 8. The three rate
select bits (SPR2:SPR1:SPR0) divide the output of the prescaler stage by 2, 4, 8, 16, 32, 64, 128, or 256
to get the internal SPI master mode bit-rate clock.
Freescale Semiconductor
BUS RATE
CLOCK
SPI SYSTEM
ENABLE
LSBFE
MSTR
SPE
SPI Baud Rate Generation
CLOCK GENERATOR
Figure
SPIBR
MASTER/SLAVE
MODE SELECT
13-4, the clock source for the SPI baud rate generator is the bus clock. The three
SHIFT
OUT
SHIFT
DIRECTION
Tx BUFFER (WRITE SPIxD)
Rx BUFFER (READ SPIxD)
MODE FAULT
DETECTION
SPI SHIFT REGISTER
CLOCK
CLOCK
LOGIC
Figure 13-3. SPI Module Block Diagram
SHIFT
MC9S08DZ128 Series Data Sheet, Rev. 1
MODF
Rx BUFFER
SPRF
FULL
Tx BUFFER
EMPTY
SHIFT
SPTEF
SPTIE
SPIE
IN
MASTER CLOCK
SLAVE CLOCK
BIDIROE
MODFEN
SPC0
SSOE
Chapter 13 Serial Peripheral Interface (S08SPIV3)
PIN CONTROL
M
S
M
S
M
S
MASTER/
SLAVE
SPI
INTERRUPT
REQUEST
MOSI
(MOMI)
MISO
(SISO)
SPSCK
SS
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