D12312SVTEBL25 Renesas Electronics America, D12312SVTEBL25 Datasheet - Page 266
![IC H8S MCU ROMLESS 100-QFP](/photos/28/61/286108/100-tqfp_sml.jpg)
D12312SVTEBL25
Manufacturer Part Number
D12312SVTEBL25
Description
IC H8S MCU ROMLESS 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of D12312SVTEBL25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412312SVTEBL25
HD6412312SVTEBL25
HD6412312SVTEBL25
- Current page: 266 of 1146
- Download datasheet (7Mb)
Section 8 I/O Ports
Pin
P12/TIOCC0/
TCLKA/A22
Rev.7.00 Feb. 14, 2007 page 232 of 1108
REJ09B0089-0700
Selection Method and Pin Functions
The pin function is switched as shown below according to the combination of
the operating mode, TPU channel 0 setting (by bits MD3 to MD0 in TMDR0,
bits IOC3 to IOC0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2
to TPSC0 in TCR0 to TCR5, bit A22E in PFCR1 and bit P12DDR.
Notes: 1. Modes 6 and 7 are not available in the ROMless versions.
Operating
Mode
TPU Channel
0 Setting
P12DDR
A22E
Pin function
TPU Channel
0 Setting
MD3 to MD0
IOC3 to IOC0
CCLR2 to
CCLR0
Output
function
2. TIOCC0 input when MD3 to MD0 = B'0000 and IOC3 to IOC0 =
3. TCLKA input when the TCR0 to TCR5 setting is: TPSC2 to TPSC0
4. TIOCD0 output is disabled.
B'10××.
= B'100.
TCLKA input when channel 1 and 5 are set to phase counting
mode (MD3 to MD0 = B'01××).
When BFA = 1 or BFB = 1 in TMDR0, output is disabled and setting
(2) applies.
Below (1)
TIOCC0
B'0000
B'0100
B'1×××
output
Table
—
—
(2)
—
—
Mode 7 *
B'0000
input
P12
—
Below (2)
TIOCC0
0
B'0001 to
B'0011
B'0101 to
B'0111
input
compare
Table
Output
output
1
(1)
output
—
P12
*
—
1
2
TIOCC0
output
—
B'001×
B'××00
0
TCLKA input *
(2)
—
—
Below (1)
Table
TIOCC0
output
0
output *
mode 1
B'0010
Modes 4 to 6 *
1
PWM
(1)
—
output
A22
1
3
Other than B'××00
4
input
P12
—
mode 2
0
output
B'101
Other
PWM
than
(1)
1
Below (2)
TIOCC0
input
B'0011
output
Table
×: Don’t care
P12
0
*
2
1
B'101
(2)
output
—
A22
1
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