D12312SVTEBL25 Renesas Electronics America, D12312SVTEBL25 Datasheet - Page 892

IC H8S MCU ROMLESS 100-QFP

D12312SVTEBL25

Manufacturer Part Number
D12312SVTEBL25
Description
IC H8S MCU ROMLESS 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets

Specifications of D12312SVTEBL25

Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412312SVTEBL25
HD6412312SVTEBL25
Section 20 Electrical Characteristics
(4) Timing of On-Chip Supporting Modules
Table 20.26 Timing of On-Chip Supporting Modules
Condition B: V
Item
I/O ports
TPU
8-bit timer
SCI
A/D
converter
Rev.7.00 Feb. 14, 2007 page 858 of 1108
REJ09B0089-0700
Output data delay time
Input data setup time
Input data hold time
Timer output delay time
Timer input setup time
Timer clock input setup time
Timer clock
pulse width
Timer output delay time
Timer reset input setup time
Timer clock input setup time
Timer clock
pulse width
Input clock
cycle
Input clock pulse width
Input clock rise time
Input clock fall time
Transmit data delay time
Receive data setup time
(synchronous)
Receive data hold time
(synchronous)
Trigger input setup time
0 V, φ = 2 MHz to 25 MHz, T
T
a
CC
= –40°C to 85°C (wide-range specifications)
= 3.0 V to 3.6 V, AV
Single-edge
specification
Both-edge
specification
Single-edge
specification
Both-edge
specification
Asynchronous
Synchronous
CC
= 3.0 V to 3.6 V, V
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
TRGS
PWD
PRS
PRH
TOCD
TICS
TCKS
TCKWH
TCKWL
TMOD
TMRS
TMCS
TMCWH
TMCWL
Scyc
SCKW
SCKr
SCKf
TXD
RXS
RXH
a
= –20°C to 75°C (regular specifications),
Min
25
25
25
25
1.5
2.5
25
25
1.5
2.5
6
0.4
40
40
30
4
ref
= 3.0 V to AV
Max
40
40
40
0.6
1.5
1.5
40
Unit
ns
ns
ns
ns
ns
ns
t
ns
ns
ns
t
t
t
t
ns
ns
ns
ns
t
t
t
t
cyc
cyc
cyc
cyc
cyc
cyc
Scyc
cyc
cyc
CC
, V
Test Conditions
Figure 20.22
Figure 20.13
Figure 20.14
Figure 20.15
Figure 20.16
Figure 20.18
Figure 20.17
Figure 20.20
Figure 20.21
SS
= AV
SS
=

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